Fast low power translation lookaside buffers using hierarchical NAND match lines

Lawrence T. Clark; Vikas Chaudhary

doi:10.1109/ISCAS.2010.5537832

Fast low power translation lookaside buffers using hierarchical NAND match lines

Lawrence T. Clark, Vikas Chaudhary

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

Translation lookaside buffers (TLB) are an essential component to speed up virtual to physical address translation in modern microprocessors. Here, hierarchical NAND content addressable memory (CAM) match lines are used to achieve low power. Simulations on a 65 nm foundry process show single-cycle accesses with a clock to physical address output delay of 168 ps. For large (16MB) page sizes the match line energy is reduced up to 81% compared to NOR match lines.

Original language	English (US)
Title of host publication	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publication	Nano-Bio Circuit Fabrics and Systems
Pages	3493-3496
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5537832
State	Published - Aug 31 2010
Event	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France Duration: May 30 2010 → Jun 2 2010

Publication series

Name	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Other

Other	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Country/Territory	France
City	Paris
Period	5/30/10 → 6/2/10

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2010.5537832

Cite this

Clark, L. T., & Chaudhary, V. (2010). Fast low power translation lookaside buffers using hierarchical NAND match lines. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 3493-3496). [5537832] (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537832

Fast low power translation lookaside buffers using hierarchical NAND match lines. / Clark, Lawrence T.; Chaudhary, Vikas.

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 3493-3496 5537832 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Clark, LT & Chaudhary, V 2010, Fast low power translation lookaside buffers using hierarchical NAND match lines. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537832, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, pp. 3493-3496, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 5/30/10. https://doi.org/10.1109/ISCAS.2010.5537832

Clark LT, Chaudhary V. Fast low power translation lookaside buffers using hierarchical NAND match lines. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 3493-3496. 5537832. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537832

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Fast low power translation lookaside buffers using hierarchical NAND match lines

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