TY - GEN
T1 - Fast low power translation lookaside buffers using hierarchical NAND match lines
AU - Clark, Lawrence T.
AU - Chaudhary, Vikas
PY - 2010/8/31
Y1 - 2010/8/31
N2 - Translation lookaside buffers (TLB) are an essential component to speed up virtual to physical address translation in modern microprocessors. Here, hierarchical NAND content addressable memory (CAM) match lines are used to achieve low power. Simulations on a 65 nm foundry process show single-cycle accesses with a clock to physical address output delay of 168 ps. For large (16MB) page sizes the match line energy is reduced up to 81% compared to NOR match lines.
AB - Translation lookaside buffers (TLB) are an essential component to speed up virtual to physical address translation in modern microprocessors. Here, hierarchical NAND content addressable memory (CAM) match lines are used to achieve low power. Simulations on a 65 nm foundry process show single-cycle accesses with a clock to physical address output delay of 168 ps. For large (16MB) page sizes the match line energy is reduced up to 81% compared to NOR match lines.
UR - http://www.scopus.com/inward/record.url?scp=77956001062&partnerID=8YFLogxK
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U2 - 10.1109/ISCAS.2010.5537832
DO - 10.1109/ISCAS.2010.5537832
M3 - Conference contribution
AN - SCOPUS:77956001062
SN - 9781424453085
T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
SP - 3493
EP - 3496
BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
T2 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Y2 - 30 May 2010 through 2 June 2010
ER -