Abstract
Translation lookaside buffers (TLB) are an essential component to speed up virtual to physical address translation in modern microprocessors. Here, hierarchical NAND content addressable memory (CAM) match lines are used to achieve low power. Simulations on a 65 nm foundry process show single-cycle accesses with a clock to physical address output delay of 168 ps. For large (16MB) page sizes the match line energy is reduced up to 81% compared to NOR match lines.
| Original language | English (US) |
|---|---|
| Title of host publication | ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems |
| Subtitle of host publication | Nano-Bio Circuit Fabrics and Systems |
| Pages | 3493-3496 |
| Number of pages | 4 |
| DOIs | |
| State | Published - Aug 31 2010 |
| Event | 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France Duration: May 30 2010 → Jun 2 2010 |
Publication series
| Name | ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems |
|---|
Other
| Other | 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 |
|---|---|
| Country | France |
| City | Paris |
| Period | 5/30/10 → 6/2/10 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
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Cite this
Clark, L. T., & Chaudhary, V. (2010). Fast low power translation lookaside buffers using hierarchical NAND match lines. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 3493-3496). [5537832] (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537832