Abstract
Translation lookaside buffers (TLB) are an essential component to speed up virtual to physical address translation in modern microprocessors. Here, hierarchical NAND content addressable memory (CAM) match lines are used to achieve low power. Simulations on a 65 nm foundry process show single-cycle accesses with a clock to physical address output delay of 168 ps. For large (16MB) page sizes the match line energy is reduced up to 81% compared to NOR match lines.
| Original language | English (US) |
|---|---|
| Title of host publication | ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems |
| Pages | 3493-3496 |
| Number of pages | 4 |
| DOIs | |
| State | Published - 2010 |
| Event | 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France Duration: May 30 2010 → Jun 2 2010 |
Other
| Other | 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 |
|---|---|
| Country | France |
| City | Paris |
| Period | 5/30/10 → 6/2/10 |
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ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
Fast low power translation lookaside buffers using hierarchical NAND match lines. / Clark, Lawrence T.; Chaudhary, Vikas.
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 3493-3496 5537832.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Fast low power translation lookaside buffers using hierarchical NAND match lines
AU - Clark, Lawrence T.
AU - Chaudhary, Vikas
PY - 2010
Y1 - 2010
N2 - Translation lookaside buffers (TLB) are an essential component to speed up virtual to physical address translation in modern microprocessors. Here, hierarchical NAND content addressable memory (CAM) match lines are used to achieve low power. Simulations on a 65 nm foundry process show single-cycle accesses with a clock to physical address output delay of 168 ps. For large (16MB) page sizes the match line energy is reduced up to 81% compared to NOR match lines.
AB - Translation lookaside buffers (TLB) are an essential component to speed up virtual to physical address translation in modern microprocessors. Here, hierarchical NAND content addressable memory (CAM) match lines are used to achieve low power. Simulations on a 65 nm foundry process show single-cycle accesses with a clock to physical address output delay of 168 ps. For large (16MB) page sizes the match line energy is reduced up to 81% compared to NOR match lines.
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UR - http://www.scopus.com/inward/citedby.url?scp=77956001062&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2010.5537832
DO - 10.1109/ISCAS.2010.5537832
M3 - Conference contribution
SN - 9781424453085
SP - 3493
EP - 3496
BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
ER -