Fast low power translation lookaside buffers using hierarchical NAND match lines

Lawrence T. Clark, Vikas Chaudhary

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Translation lookaside buffers (TLB) are an essential component to speed up virtual to physical address translation in modern microprocessors. Here, hierarchical NAND content addressable memory (CAM) match lines are used to achieve low power. Simulations on a 65 nm foundry process show single-cycle accesses with a clock to physical address output delay of 168 ps. For large (16MB) page sizes the match line energy is reduced up to 81% compared to NOR match lines.

Original languageEnglish (US)
Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publicationNano-Bio Circuit Fabrics and Systems
Pages3493-3496
Number of pages4
DOIs
StatePublished - Aug 31 2010
Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
Duration: May 30 2010Jun 2 2010

Publication series

NameISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Other

Other2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
CountryFrance
CityParis
Period5/30/106/2/10

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Clark, L. T., & Chaudhary, V. (2010). Fast low power translation lookaside buffers using hierarchical NAND match lines. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 3493-3496). [5537832] (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537832