Fast hierarchical process variability analysis and parametric test development for analog/RF circuits

Fang Liu, Sule Ozev

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

The test development efforts for analog/RF circuits in computer systems today are disproportionately high due to the lack of widely accepted automation methods. The evaluation of a particular test input and measurement set-up requires the determination of the probabilistic detection of all faults in the circuit. This evaluation step is the most time consuming step during analog test development. Based on the observation that test evaluation requires injecting many parametric deviations into the circuit and analyzing the masking effect of process variations, we develop a hierarchical process variability analysis technique for analog/RF circuits that is specifically geared towards information re-use. We also present a heuristic test selection methodology that aims at providing the same coverage level as the full specification measurements while reducing the test time as well as reliance on hard-to-measure parameters. Experimental results on a differential amplifier circuit confirm the high accuracy of our variance analysis technique and show a 57% reduction in the number of tests after the application of the test selection algorithm.

Original languageEnglish (US)
Title of host publicationProceedings - 2005 IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors, ICCD 2005
Pages161-168
Number of pages8
DOIs
StatePublished - Dec 1 2005
Externally publishedYes
Event2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 - San Jose, CA, United States
Duration: Oct 2 2005Oct 5 2005

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Volume2005
ISSN (Print)1063-6404

Other

Other2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005
CountryUnited States
CitySan Jose, CA
Period10/2/0510/5/05

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Liu, F., & Ozev, S. (2005). Fast hierarchical process variability analysis and parametric test development for analog/RF circuits. In Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 (pp. 161-168). [1524148] (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors; Vol. 2005). https://doi.org/10.1109/ICCD.2005.54