Fast and robust differential flipflops and their extension to multi-input threshold gates

Jinghua Yang, Niranjan Kulkarni, Joseph Davis, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, we describe two single input threshold gate (TLG) designs, which are functionally equivalent to differential flipflops. We present a detailed comparison of TLGs with two well established D-flipflop designs. The comparisons are done in both 65nm and 28nm commercial processes. We compare total delay, which is defined as the sum of setup delay and clock to output delay. We also show a comparison of tolerance against noise and process variation between the different designs. The two proposed designs are found to be as robust as an existing D-flipflop from both commercial standard cell libraries. Meanwhile, they are 33% and 25% faster in 65nm post-layout and 25% and 22% faster in 28nm post-layout compared to a commercial D-flipflop. The energy delay product of two proposed designs is 46% and 25% smaller in the 28nm process post layout simulation. Single input threshold gates can also be extended to multi-input threshold gates. We compare the total delay, power and leakage of a three-input threshold gate as well as a seven-input threshold gate with those of the equivalent (Complementary Metal Oxide Semiconductor) CMOS counterpart, which shows 52% 48% improvement in 65nm and 35% speed improvement in the 28nm process.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages822-825
Number of pages4
Volume2015-July
ISBN (Print)9781479983919
DOIs
StatePublished - Jul 27 2015
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: May 24 2015May 27 2015

Other

OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015
CountryPortugal
CityLisbon
Period5/24/155/27/15

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Oxide semiconductors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Yang, J., Kulkarni, N., Davis, J., & Vrudhula, S. (2015). Fast and robust differential flipflops and their extension to multi-input threshold gates. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 2015-July, pp. 822-825). [7168760] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7168760

Fast and robust differential flipflops and their extension to multi-input threshold gates. / Yang, Jinghua; Kulkarni, Niranjan; Davis, Joseph; Vrudhula, Sarma.

Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July Institute of Electrical and Electronics Engineers Inc., 2015. p. 822-825 7168760.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yang, J, Kulkarni, N, Davis, J & Vrudhula, S 2015, Fast and robust differential flipflops and their extension to multi-input threshold gates. in Proceedings - IEEE International Symposium on Circuits and Systems. vol. 2015-July, 7168760, Institute of Electrical and Electronics Engineers Inc., pp. 822-825, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 5/24/15. https://doi.org/10.1109/ISCAS.2015.7168760
Yang J, Kulkarni N, Davis J, Vrudhula S. Fast and robust differential flipflops and their extension to multi-input threshold gates. In Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July. Institute of Electrical and Electronics Engineers Inc. 2015. p. 822-825. 7168760 https://doi.org/10.1109/ISCAS.2015.7168760
Yang, Jinghua ; Kulkarni, Niranjan ; Davis, Joseph ; Vrudhula, Sarma. / Fast and robust differential flipflops and their extension to multi-input threshold gates. Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July Institute of Electrical and Electronics Engineers Inc., 2015. pp. 822-825
@inproceedings{6760ae601d2b4053a8c9ee3f90f6cde7,
title = "Fast and robust differential flipflops and their extension to multi-input threshold gates",
abstract = "In this paper, we describe two single input threshold gate (TLG) designs, which are functionally equivalent to differential flipflops. We present a detailed comparison of TLGs with two well established D-flipflop designs. The comparisons are done in both 65nm and 28nm commercial processes. We compare total delay, which is defined as the sum of setup delay and clock to output delay. We also show a comparison of tolerance against noise and process variation between the different designs. The two proposed designs are found to be as robust as an existing D-flipflop from both commercial standard cell libraries. Meanwhile, they are 33{\%} and 25{\%} faster in 65nm post-layout and 25{\%} and 22{\%} faster in 28nm post-layout compared to a commercial D-flipflop. The energy delay product of two proposed designs is 46{\%} and 25{\%} smaller in the 28nm process post layout simulation. Single input threshold gates can also be extended to multi-input threshold gates. We compare the total delay, power and leakage of a three-input threshold gate as well as a seven-input threshold gate with those of the equivalent (Complementary Metal Oxide Semiconductor) CMOS counterpart, which shows 52{\%} 48{\%} improvement in 65nm and 35{\%} speed improvement in the 28nm process.",
author = "Jinghua Yang and Niranjan Kulkarni and Joseph Davis and Sarma Vrudhula",
year = "2015",
month = "7",
day = "27",
doi = "10.1109/ISCAS.2015.7168760",
language = "English (US)",
isbn = "9781479983919",
volume = "2015-July",
pages = "822--825",
booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - Fast and robust differential flipflops and their extension to multi-input threshold gates

AU - Yang, Jinghua

AU - Kulkarni, Niranjan

AU - Davis, Joseph

AU - Vrudhula, Sarma

PY - 2015/7/27

Y1 - 2015/7/27

N2 - In this paper, we describe two single input threshold gate (TLG) designs, which are functionally equivalent to differential flipflops. We present a detailed comparison of TLGs with two well established D-flipflop designs. The comparisons are done in both 65nm and 28nm commercial processes. We compare total delay, which is defined as the sum of setup delay and clock to output delay. We also show a comparison of tolerance against noise and process variation between the different designs. The two proposed designs are found to be as robust as an existing D-flipflop from both commercial standard cell libraries. Meanwhile, they are 33% and 25% faster in 65nm post-layout and 25% and 22% faster in 28nm post-layout compared to a commercial D-flipflop. The energy delay product of two proposed designs is 46% and 25% smaller in the 28nm process post layout simulation. Single input threshold gates can also be extended to multi-input threshold gates. We compare the total delay, power and leakage of a three-input threshold gate as well as a seven-input threshold gate with those of the equivalent (Complementary Metal Oxide Semiconductor) CMOS counterpart, which shows 52% 48% improvement in 65nm and 35% speed improvement in the 28nm process.

AB - In this paper, we describe two single input threshold gate (TLG) designs, which are functionally equivalent to differential flipflops. We present a detailed comparison of TLGs with two well established D-flipflop designs. The comparisons are done in both 65nm and 28nm commercial processes. We compare total delay, which is defined as the sum of setup delay and clock to output delay. We also show a comparison of tolerance against noise and process variation between the different designs. The two proposed designs are found to be as robust as an existing D-flipflop from both commercial standard cell libraries. Meanwhile, they are 33% and 25% faster in 65nm post-layout and 25% and 22% faster in 28nm post-layout compared to a commercial D-flipflop. The energy delay product of two proposed designs is 46% and 25% smaller in the 28nm process post layout simulation. Single input threshold gates can also be extended to multi-input threshold gates. We compare the total delay, power and leakage of a three-input threshold gate as well as a seven-input threshold gate with those of the equivalent (Complementary Metal Oxide Semiconductor) CMOS counterpart, which shows 52% 48% improvement in 65nm and 35% speed improvement in the 28nm process.

UR - http://www.scopus.com/inward/record.url?scp=84946238903&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84946238903&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2015.7168760

DO - 10.1109/ISCAS.2015.7168760

M3 - Conference contribution

AN - SCOPUS:84946238903

SN - 9781479983919

VL - 2015-July

SP - 822

EP - 825

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

ER -