In this paper, we describe two single input threshold gate (TLG) designs, which are functionally equivalent to differential flipflops. We present a detailed comparison of TLGs with two well established D-flipflop designs. The comparisons are done in both 65nm and 28nm commercial processes. We compare total delay, which is defined as the sum of setup delay and clock to output delay. We also show a comparison of tolerance against noise and process variation between the different designs. The two proposed designs are found to be as robust as an existing D-flipflop from both commercial standard cell libraries. Meanwhile, they are 33% and 25% faster in 65nm post-layout and 25% and 22% faster in 28nm post-layout compared to a commercial D-flipflop. The energy delay product of two proposed designs is 46% and 25% smaller in the 28nm process post layout simulation. Single input threshold gates can also be extended to multi-input threshold gates. We compare the total delay, power and leakage of a three-input threshold gate as well as a seven-input threshold gate with those of the equivalent (Complementary Metal Oxide Semiconductor) CMOS counterpart, which shows 52% 48% improvement in 65nm and 35% speed improvement in the 28nm process.