This paper describes a fast and accurate technique to predict the steady-state throughput and the corresponding power consumption of a homogeneous multicore processor for a given benchmark workload while accounting for speed reduction due to thermal constraints. The expressions contain several parameters of interest to a system designer, like the static and dynamic-power consumptions (for hottest block and for full chip), the vertical thermal resistance of the hottest block, the leakage sensitivity to temperature, the chip threshold temperature, the ambient temperature, etc. Their computational complexity is independent of the number of cores. These are incorporated in a system-level multicore power/thermal simulator that uses the PTScalar power model and the Hotspot thermal model. The analytical throughput and power predictions were within 1.7% of that predicted by the system-level simulator. However, the analytical technique takes less than 0.2 s for a given set of design parameters, making it well suited for early design-space exploration. In contrast, the numerical technique takes anywhere from a minute (for 4 cores) up to a few hours (for 25 cores).
|Original language||English (US)|
|Number of pages||14|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|State||Published - Oct 1 2009|
- Dynamic thermal management (DTM)
- Frequency scaling
- Multicore processors
- Power management
- Throughput optimization.
ASJC Scopus subject areas
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering