Fabrication of sub-20 nm nanopore arrays in membranes with embedded metal electrodes at wafer scales

Jingwei Bai, Deqiang Wang, Sung Wook Nam, Hongbo Peng, Robert Bruce, Lynn Gignac, Markus Brink, Ernst Kratschmer, Stephen Rossnagel, Phil Waggoner, Kathleen Reuter, Chao Wang, Yann Astier, Venkat Balagurusamy, Binquan Luan, Young Kwark, Eric Joseph, Mike Guillorn, Stanislav Polonsky, Ajay Royyuru & 2 others S. Papa Rao, Gustavo Stolovitzky

Research output: Contribution to journalArticle

38 Citations (Scopus)

Abstract

We introduce a method to fabricate solid-state nanopores with sub-20 nm diameter in membranes with embedded metal electrodes across a 200 mm wafer using CMOS compatible semiconductor processes. Multi-layer (metal-dielectric) structures embedded in membranes were demonstrated to have high uniformity (±0.5 nm) across the wafer. Arrays of nanopores were fabricated with an average size of 18 ± 2 nm in diameter using a Reactive Ion Etching (RIE) method in lieu of TEM drilling. Shorts between the membrane-embedded metals were occasionally created after pore formation, but the RIE based pores had a much better yield (99%) of unshorted electrodes compared to TEM drilled pores (

Original languageEnglish (US)
Pages (from-to)8900-8906
Number of pages7
JournalNanoscale
Volume6
Issue number15
DOIs
StatePublished - Aug 7 2014
Externally publishedYes

Fingerprint

Nanopores
Metals
Reactive ion etching
Membranes
Fabrication
Electrodes
Transmission electron microscopy
Drilling
Semiconductor materials

ASJC Scopus subject areas

  • Materials Science(all)

Cite this

Bai, J., Wang, D., Nam, S. W., Peng, H., Bruce, R., Gignac, L., ... Stolovitzky, G. (2014). Fabrication of sub-20 nm nanopore arrays in membranes with embedded metal electrodes at wafer scales. Nanoscale, 6(15), 8900-8906. https://doi.org/10.1039/c3nr06723h

Fabrication of sub-20 nm nanopore arrays in membranes with embedded metal electrodes at wafer scales. / Bai, Jingwei; Wang, Deqiang; Nam, Sung Wook; Peng, Hongbo; Bruce, Robert; Gignac, Lynn; Brink, Markus; Kratschmer, Ernst; Rossnagel, Stephen; Waggoner, Phil; Reuter, Kathleen; Wang, Chao; Astier, Yann; Balagurusamy, Venkat; Luan, Binquan; Kwark, Young; Joseph, Eric; Guillorn, Mike; Polonsky, Stanislav; Royyuru, Ajay; Papa Rao, S.; Stolovitzky, Gustavo.

In: Nanoscale, Vol. 6, No. 15, 07.08.2014, p. 8900-8906.

Research output: Contribution to journalArticle

Bai, J, Wang, D, Nam, SW, Peng, H, Bruce, R, Gignac, L, Brink, M, Kratschmer, E, Rossnagel, S, Waggoner, P, Reuter, K, Wang, C, Astier, Y, Balagurusamy, V, Luan, B, Kwark, Y, Joseph, E, Guillorn, M, Polonsky, S, Royyuru, A, Papa Rao, S & Stolovitzky, G 2014, 'Fabrication of sub-20 nm nanopore arrays in membranes with embedded metal electrodes at wafer scales', Nanoscale, vol. 6, no. 15, pp. 8900-8906. https://doi.org/10.1039/c3nr06723h
Bai, Jingwei ; Wang, Deqiang ; Nam, Sung Wook ; Peng, Hongbo ; Bruce, Robert ; Gignac, Lynn ; Brink, Markus ; Kratschmer, Ernst ; Rossnagel, Stephen ; Waggoner, Phil ; Reuter, Kathleen ; Wang, Chao ; Astier, Yann ; Balagurusamy, Venkat ; Luan, Binquan ; Kwark, Young ; Joseph, Eric ; Guillorn, Mike ; Polonsky, Stanislav ; Royyuru, Ajay ; Papa Rao, S. ; Stolovitzky, Gustavo. / Fabrication of sub-20 nm nanopore arrays in membranes with embedded metal electrodes at wafer scales. In: Nanoscale. 2014 ; Vol. 6, No. 15. pp. 8900-8906.
@article{98386517c74d48408aa2fc867766c0b6,
title = "Fabrication of sub-20 nm nanopore arrays in membranes with embedded metal electrodes at wafer scales",
abstract = "We introduce a method to fabricate solid-state nanopores with sub-20 nm diameter in membranes with embedded metal electrodes across a 200 mm wafer using CMOS compatible semiconductor processes. Multi-layer (metal-dielectric) structures embedded in membranes were demonstrated to have high uniformity (±0.5 nm) across the wafer. Arrays of nanopores were fabricated with an average size of 18 ± 2 nm in diameter using a Reactive Ion Etching (RIE) method in lieu of TEM drilling. Shorts between the membrane-embedded metals were occasionally created after pore formation, but the RIE based pores had a much better yield (99{\%}) of unshorted electrodes compared to TEM drilled pores (",
author = "Jingwei Bai and Deqiang Wang and Nam, {Sung Wook} and Hongbo Peng and Robert Bruce and Lynn Gignac and Markus Brink and Ernst Kratschmer and Stephen Rossnagel and Phil Waggoner and Kathleen Reuter and Chao Wang and Yann Astier and Venkat Balagurusamy and Binquan Luan and Young Kwark and Eric Joseph and Mike Guillorn and Stanislav Polonsky and Ajay Royyuru and {Papa Rao}, S. and Gustavo Stolovitzky",
year = "2014",
month = "8",
day = "7",
doi = "10.1039/c3nr06723h",
language = "English (US)",
volume = "6",
pages = "8900--8906",
journal = "Nanoscale",
issn = "2040-3364",
publisher = "Royal Society of Chemistry",
number = "15",

}

TY - JOUR

T1 - Fabrication of sub-20 nm nanopore arrays in membranes with embedded metal electrodes at wafer scales

AU - Bai, Jingwei

AU - Wang, Deqiang

AU - Nam, Sung Wook

AU - Peng, Hongbo

AU - Bruce, Robert

AU - Gignac, Lynn

AU - Brink, Markus

AU - Kratschmer, Ernst

AU - Rossnagel, Stephen

AU - Waggoner, Phil

AU - Reuter, Kathleen

AU - Wang, Chao

AU - Astier, Yann

AU - Balagurusamy, Venkat

AU - Luan, Binquan

AU - Kwark, Young

AU - Joseph, Eric

AU - Guillorn, Mike

AU - Polonsky, Stanislav

AU - Royyuru, Ajay

AU - Papa Rao, S.

AU - Stolovitzky, Gustavo

PY - 2014/8/7

Y1 - 2014/8/7

N2 - We introduce a method to fabricate solid-state nanopores with sub-20 nm diameter in membranes with embedded metal electrodes across a 200 mm wafer using CMOS compatible semiconductor processes. Multi-layer (metal-dielectric) structures embedded in membranes were demonstrated to have high uniformity (±0.5 nm) across the wafer. Arrays of nanopores were fabricated with an average size of 18 ± 2 nm in diameter using a Reactive Ion Etching (RIE) method in lieu of TEM drilling. Shorts between the membrane-embedded metals were occasionally created after pore formation, but the RIE based pores had a much better yield (99%) of unshorted electrodes compared to TEM drilled pores (

AB - We introduce a method to fabricate solid-state nanopores with sub-20 nm diameter in membranes with embedded metal electrodes across a 200 mm wafer using CMOS compatible semiconductor processes. Multi-layer (metal-dielectric) structures embedded in membranes were demonstrated to have high uniformity (±0.5 nm) across the wafer. Arrays of nanopores were fabricated with an average size of 18 ± 2 nm in diameter using a Reactive Ion Etching (RIE) method in lieu of TEM drilling. Shorts between the membrane-embedded metals were occasionally created after pore formation, but the RIE based pores had a much better yield (99%) of unshorted electrodes compared to TEM drilled pores (

UR - http://www.scopus.com/inward/record.url?scp=84904288670&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84904288670&partnerID=8YFLogxK

U2 - 10.1039/c3nr06723h

DO - 10.1039/c3nr06723h

M3 - Article

VL - 6

SP - 8900

EP - 8906

JO - Nanoscale

JF - Nanoscale

SN - 2040-3364

IS - 15

ER -