TY - GEN
T1 - Extending energy-saving voltage scaling in ultra low voltage integrated circuit designs
AU - Seok, Mingoo
AU - Jeon, Dongsuk
AU - Chakrabati, Chaitali
AU - Blaauw, David
AU - Sylvester, Dennis
PY - 2012
Y1 - 2012
N2 - In this paper, we propose several design approaches to extend useful voltage scaling (i.e. voltage scaling with net energy savings) beyond the conventional limit, which is imposed by the rapid increase of leakage energy overhead in ultra low voltage regimes. We are able to achieve such extra voltage scaling and thus energy savings without compromising performance and variability through minimizing the ratio of leakage to dynamic energy in a circuit. Novel design approaches in pipeline, clocking and architecture optimization are investigated; and applied during the design of a 16b 1024pt complex FFT core. The measurement results from the prototyped FFT core in a 65nm CMOS show the energy consumption of 15.8nF/FFF with the clock frequency of 30MHz and the throughput of 240Msamples/s at the supply voltage of 270mV, which exhibits 2.4× higher energy efficiency and >10× higher throughput than the previous low power FFT designs. Measurement of 60 dies shows modest frequency and energy σ/μ spreads of 7% and 2%, respectively.
AB - In this paper, we propose several design approaches to extend useful voltage scaling (i.e. voltage scaling with net energy savings) beyond the conventional limit, which is imposed by the rapid increase of leakage energy overhead in ultra low voltage regimes. We are able to achieve such extra voltage scaling and thus energy savings without compromising performance and variability through minimizing the ratio of leakage to dynamic energy in a circuit. Novel design approaches in pipeline, clocking and architecture optimization are investigated; and applied during the design of a 16b 1024pt complex FFT core. The measurement results from the prototyped FFT core in a 65nm CMOS show the energy consumption of 15.8nF/FFF with the clock frequency of 30MHz and the throughput of 240Msamples/s at the supply voltage of 270mV, which exhibits 2.4× higher energy efficiency and >10× higher throughput than the previous low power FFT designs. Measurement of 60 dies shows modest frequency and energy σ/μ spreads of 7% and 2%, respectively.
KW - FFT core
KW - energy-optimal FFT architecture
KW - less-buffered clock networks
KW - super-pipelining
KW - two-phase latch-based design
KW - ultra low power
KW - ultra low voltage
KW - useful voltage scaling
UR - http://www.scopus.com/inward/record.url?scp=84864692623&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84864692623&partnerID=8YFLogxK
U2 - 10.1109/ICICDT.2012.6232880
DO - 10.1109/ICICDT.2012.6232880
M3 - Conference contribution
AN - SCOPUS:84864692623
SN - 9781467301466
T3 - ICICDT 2012 - IEEE International Conference on Integrated Circuit Design and Technology
BT - ICICDT 2012 - IEEE International Conference on Integrated Circuit Design and Technology
T2 - IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2012
Y2 - 30 May 2012 through 1 June 2012
ER -