Experimental validation of self-heating simulations and projections for transistors in deeply scaled nodes

E. Bury, B. Kaczer, P. Roussel, R. Ritzenthaler, K. Raleva, Dragica Vasileska, G. Groeseneken

Research output: Chapter in Book/Report/Conference proceedingConference contribution

28 Scopus citations

Abstract

CMOS device improvements have recently been achieved by changing the geometry of the device from planar to fully-depleted (FD) FinFET. Also FD SOI (Silicon-on-Isolator) devices have emerged as a candidate for replacing bulk silicon in ULSI applications in future technology nodes. Along with this scaling comes, however, a challenging penalty: device self-heating. In this study, i) we propose a unique measurement technique for self-heating and use it to assess self-heating in planar devices, ii) we compare and verify these results with finite-element simulations and iii) we provide perspectives for upcoming FinFET nodes.

Original languageEnglish (US)
Title of host publication2014 IEEE International Reliability Physics Symposium, IRPS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesXT.8.1-XT.8.6
ISBN (Print)9781479933167
DOIs
StatePublished - Jan 1 2014
Event52nd IEEE International Reliability Physics Symposium, IRPS 2014 - Waikoloa, HI, United States
Duration: Jun 1 2014Jun 5 2014

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Other

Other52nd IEEE International Reliability Physics Symposium, IRPS 2014
Country/TerritoryUnited States
CityWaikoloa, HI
Period6/1/146/5/14

Keywords

  • EKV
  • FinFET
  • SHE
  • reliability
  • self-heating

ASJC Scopus subject areas

  • Engineering(all)

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