Experimental characterization and application of circuit architecture level single event transient mitigation

Karl C. Mohr, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

In this work experimental characterization of process single event transient (SET) performance as a function of circuit node capacitance and. drive strength is described. A test structure fabricated on a 130 nm bulk CMOS process is described. Experimental results from ion beam measurements on the structure are also presented. The results can be used early in the design cycle to limit reliability impact due to S1ETs. An SRAM design example demonstrates how measured SET data can be used to trade off dynamic power dissipation for improved soft error performance without increasing circuit area.

Original languageEnglish (US)
Title of host publication2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual
Pages312-317
Number of pages6
DOIs
StatePublished - Sep 25 2007
Event45th Annual IEEE International Reliability Physics Symposium 2007, IRPS - Phoenix, AZ, United States
Duration: Apr 15 2007Apr 19 2007

Publication series

NameAnnual Proceedings - Reliability Physics (Symposium)
ISSN (Print)0099-9512

Other

Other45th Annual IEEE International Reliability Physics Symposium 2007, IRPS
CountryUnited States
CityPhoenix, AZ
Period4/15/074/19/07

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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    Mohr, K. C., & Clark, L. T. (2007). Experimental characterization and application of circuit architecture level single event transient mitigation. In 2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual (pp. 312-317). [4227650] (Annual Proceedings - Reliability Physics (Symposium)). https://doi.org/10.1109/RELPHY.2007.369909