@inproceedings{da74059c35bc40a19a6b4ee6e8119960,
title = "Experimental characterization and application of circuit architecture level single event transient mitigation",
abstract = "In this work experimental characterization of process single event transient (SET) performance as a function of circuit node capacitance and. drive strength is described. A test structure fabricated on a 130 nm bulk CMOS process is described. Experimental results from ion beam measurements on the structure are also presented. The results can be used early in the design cycle to limit reliability impact due to S1ETs. An SRAM design example demonstrates how measured SET data can be used to trade off dynamic power dissipation for improved soft error performance without increasing circuit area.",
author = "Mohr, {Karl C.} and Clark, {Lawrence T.}",
year = "2007",
doi = "10.1109/RELPHY.2007.369909",
language = "English (US)",
isbn = "1424409195",
series = "Annual Proceedings - Reliability Physics (Symposium)",
pages = "312--317",
booktitle = "2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual",
note = "45th Annual IEEE International Reliability Physics Symposium 2007, IRPS ; Conference date: 15-04-2007 Through 19-04-2007",
}