Experimental characterization and application of circuit architecture level single event transient mitigation

Karl C. Mohr, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

In this work experimental characterization of process single event transient (SET) performance as a function of circuit node capacitance and. drive strength is described. A test structure fabricated on a 130 nm bulk CMOS process is described. Experimental results from ion beam measurements on the structure are also presented. The results can be used early in the design cycle to limit reliability impact due to S1ETs. An SRAM design example demonstrates how measured SET data can be used to trade off dynamic power dissipation for improved soft error performance without increasing circuit area.

Original languageEnglish (US)
Title of host publicationAnnual Proceedings - Reliability Physics (Symposium)
Pages312-317
Number of pages6
DOIs
StatePublished - 2007
Event45th Annual IEEE International Reliability Physics Symposium 2007, IRPS - Phoenix, AZ, United States
Duration: Apr 15 2007Apr 19 2007

Other

Other45th Annual IEEE International Reliability Physics Symposium 2007, IRPS
CountryUnited States
CityPhoenix, AZ
Period4/15/074/19/07

Fingerprint

Networks (circuits)
Static random access storage
Ion beams
Energy dissipation
Capacitance

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Mohr, K. C., & Clark, L. T. (2007). Experimental characterization and application of circuit architecture level single event transient mitigation. In Annual Proceedings - Reliability Physics (Symposium) (pp. 312-317). [4227650] https://doi.org/10.1109/RELPHY.2007.369909

Experimental characterization and application of circuit architecture level single event transient mitigation. / Mohr, Karl C.; Clark, Lawrence T.

Annual Proceedings - Reliability Physics (Symposium). 2007. p. 312-317 4227650.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Mohr, KC & Clark, LT 2007, Experimental characterization and application of circuit architecture level single event transient mitigation. in Annual Proceedings - Reliability Physics (Symposium)., 4227650, pp. 312-317, 45th Annual IEEE International Reliability Physics Symposium 2007, IRPS, Phoenix, AZ, United States, 4/15/07. https://doi.org/10.1109/RELPHY.2007.369909
Mohr KC, Clark LT. Experimental characterization and application of circuit architecture level single event transient mitigation. In Annual Proceedings - Reliability Physics (Symposium). 2007. p. 312-317. 4227650 https://doi.org/10.1109/RELPHY.2007.369909
Mohr, Karl C. ; Clark, Lawrence T. / Experimental characterization and application of circuit architecture level single event transient mitigation. Annual Proceedings - Reliability Physics (Symposium). 2007. pp. 312-317
@inproceedings{da74059c35bc40a19a6b4ee6e8119960,
title = "Experimental characterization and application of circuit architecture level single event transient mitigation",
abstract = "In this work experimental characterization of process single event transient (SET) performance as a function of circuit node capacitance and. drive strength is described. A test structure fabricated on a 130 nm bulk CMOS process is described. Experimental results from ion beam measurements on the structure are also presented. The results can be used early in the design cycle to limit reliability impact due to S1ETs. An SRAM design example demonstrates how measured SET data can be used to trade off dynamic power dissipation for improved soft error performance without increasing circuit area.",
author = "Mohr, {Karl C.} and Clark, {Lawrence T.}",
year = "2007",
doi = "10.1109/RELPHY.2007.369909",
language = "English (US)",
isbn = "1424409195",
pages = "312--317",
booktitle = "Annual Proceedings - Reliability Physics (Symposium)",

}

TY - GEN

T1 - Experimental characterization and application of circuit architecture level single event transient mitigation

AU - Mohr, Karl C.

AU - Clark, Lawrence T.

PY - 2007

Y1 - 2007

N2 - In this work experimental characterization of process single event transient (SET) performance as a function of circuit node capacitance and. drive strength is described. A test structure fabricated on a 130 nm bulk CMOS process is described. Experimental results from ion beam measurements on the structure are also presented. The results can be used early in the design cycle to limit reliability impact due to S1ETs. An SRAM design example demonstrates how measured SET data can be used to trade off dynamic power dissipation for improved soft error performance without increasing circuit area.

AB - In this work experimental characterization of process single event transient (SET) performance as a function of circuit node capacitance and. drive strength is described. A test structure fabricated on a 130 nm bulk CMOS process is described. Experimental results from ion beam measurements on the structure are also presented. The results can be used early in the design cycle to limit reliability impact due to S1ETs. An SRAM design example demonstrates how measured SET data can be used to trade off dynamic power dissipation for improved soft error performance without increasing circuit area.

UR - http://www.scopus.com/inward/record.url?scp=34548749847&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34548749847&partnerID=8YFLogxK

U2 - 10.1109/RELPHY.2007.369909

DO - 10.1109/RELPHY.2007.369909

M3 - Conference contribution

AN - SCOPUS:34548749847

SN - 1424409195

SN - 9781424409198

SP - 312

EP - 317

BT - Annual Proceedings - Reliability Physics (Symposium)

ER -