TY - GEN
T1 - Experiences using a novel Python-based hardware modeling framework for computer architecture test chips.
AU - Torng, Christopher
AU - Wang, Moyang
AU - Sudheendra, Bharath
AU - Murali, Nagaraj
AU - Jayasuriya, Suren
AU - Srinath, Shreesha
AU - Pritchard, Taylor
AU - Ying, Robin
AU - Batten, Christopher
N1 - Funding Information:
Chip fabrication was made possible by the MOSIS Educational Program. This work was supported in part by NSF CAREER Award #1149464, NSF XPS Award #1337240, NSF CRI Award #1512937, and equipment/tool/IP donations from Intel, Synopsys, Cadence, Mentor Graphics, Xilinx, and ARM.
Publisher Copyright:
© 2016 IEEE.
PY - 2017/5/30
Y1 - 2017/5/30
N2 - This poster will describe a taped-out 2×2mm 1.3 M-transistor test chip in IBM 130 nm designed using our new Python-based hardware modeling framework. The goal of our tapeout was to demonstrate the ability of this framework to enable Agile hardware design flows.
AB - This poster will describe a taped-out 2×2mm 1.3 M-transistor test chip in IBM 130 nm designed using our new Python-based hardware modeling framework. The goal of our tapeout was to demonstrate the ability of this framework to enable Agile hardware design flows.
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U2 - 10.1109/HOTCHIPS.2016.7936233
DO - 10.1109/HOTCHIPS.2016.7936233
M3 - Conference contribution
AN - SCOPUS:85025805486
T3 - 2016 IEEE Hot Chips 28 Symposium, HCS 2016
BT - 2016 IEEE Hot Chips 28 Symposium, HCS 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 28th IEEE Hot Chips Symposium, HCS 2016
Y2 - 21 August 2016 through 23 August 2016
ER -