Experiences using a novel Python-based hardware modeling framework for computer architecture test chips.

Christopher Torng; Moyang Wang; Bharath Sudheendra; Nagaraj Murali; Suren Jayasuriya; Shreesha Srinath; Taylor Pritchard; Robin Ying; Christopher Batten

doi:10.1109/HOTCHIPS.2016.7936233

Experiences using a novel Python-based hardware modeling framework for computer architecture test chips.

Christopher Torng, Moyang Wang, Bharath Sudheendra, Nagaraj Murali, Suren Jayasuriya, Shreesha Srinath, Taylor Pritchard, Robin Ying, Christopher Batten

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This poster will describe a taped-out 2×2mm 1.3 M-transistor test chip in IBM 130 nm designed using our new Python-based hardware modeling framework. The goal of our tapeout was to demonstrate the ability of this framework to enable Agile hardware design flows.

Original language	English (US)
Title of host publication	2016 IEEE Hot Chips 28 Symposium, HCS 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509062089
DOIs	https://doi.org/10.1109/HOTCHIPS.2016.7936233
State	Published - May 30 2017
Externally published	Yes
Event	28th IEEE Hot Chips Symposium, HCS 2016 - Cupertino, United States Duration: Aug 21 2016 → Aug 23 2016

Publication series

Name	2016 IEEE Hot Chips 28 Symposium, HCS 2016

Other

Other	28th IEEE Hot Chips Symposium, HCS 2016
Country/Territory	United States
City	Cupertino
Period	8/21/16 → 8/23/16

ASJC Scopus subject areas

Hardware and Architecture

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10.1109/HOTCHIPS.2016.7936233

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Torng, C., Wang, M., Sudheendra, B., Murali, N., Jayasuriya, S., Srinath, S., Pritchard, T., Ying, R., & Batten, C. (2017). Experiences using a novel Python-based hardware modeling framework for computer architecture test chips. In 2016 IEEE Hot Chips 28 Symposium, HCS 2016 Article 7936233 (2016 IEEE Hot Chips 28 Symposium, HCS 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/HOTCHIPS.2016.7936233

Experiences using a novel Python-based hardware modeling framework for computer architecture test chips. / Torng, Christopher; Wang, Moyang; Sudheendra, Bharath et al.
2016 IEEE Hot Chips 28 Symposium, HCS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. 7936233 (2016 IEEE Hot Chips 28 Symposium, HCS 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Torng, C, Wang, M, Sudheendra, B, Murali, N, Jayasuriya, S, Srinath, S, Pritchard, T, Ying, R & Batten, C 2017, Experiences using a novel Python-based hardware modeling framework for computer architecture test chips. in 2016 IEEE Hot Chips 28 Symposium, HCS 2016., 7936233, 2016 IEEE Hot Chips 28 Symposium, HCS 2016, Institute of Electrical and Electronics Engineers Inc., 28th IEEE Hot Chips Symposium, HCS 2016, Cupertino, United States, 8/21/16. https://doi.org/10.1109/HOTCHIPS.2016.7936233

Torng C, Wang M, Sudheendra B, Murali N, Jayasuriya S, Srinath S et al. Experiences using a novel Python-based hardware modeling framework for computer architecture test chips. In 2016 IEEE Hot Chips 28 Symposium, HCS 2016. Institute of Electrical and Electronics Engineers Inc. 2017. 7936233. (2016 IEEE Hot Chips 28 Symposium, HCS 2016). doi: 10.1109/HOTCHIPS.2016.7936233

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Experiences using a novel Python-based hardware modeling framework for computer architecture test chips.

Abstract

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ASJC Scopus subject areas

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