Experiences using a novel Python-based hardware modeling framework for computer architecture test chips.

Christopher Torng, Moyang Wang, Bharath Sudheendra, Nagaraj Murali, Suren Jayasuriya, Shreesha Srinath, Taylor Pritchard, Robin Ying, Christopher Batten

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This poster will describe a taped-out 2×2mm 1.3 M-transistor test chip in IBM 130 nm designed using our new Python-based hardware modeling framework. The goal of our tapeout was to demonstrate the ability of this framework to enable Agile hardware design flows.

Original languageEnglish (US)
Title of host publication2016 IEEE Hot Chips 28 Symposium, HCS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509062089
DOIs
StatePublished - May 30 2017
Externally publishedYes
Event28th IEEE Hot Chips Symposium, HCS 2016 - Cupertino, United States
Duration: Aug 21 2016Aug 23 2016

Other

Other28th IEEE Hot Chips Symposium, HCS 2016
CountryUnited States
CityCupertino
Period8/21/168/23/16

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ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Torng, C., Wang, M., Sudheendra, B., Murali, N., Jayasuriya, S., Srinath, S., Pritchard, T., Ying, R., & Batten, C. (2017). Experiences using a novel Python-based hardware modeling framework for computer architecture test chips. In 2016 IEEE Hot Chips 28 Symposium, HCS 2016 [7936233] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/HOTCHIPS.2016.7936233