Abstract
This paper investigates the design of evolvable FPGA circuits where the design space is severely constrained to an interconnected network of meaningful high-level operators. The specific design domain is image processing, especially pattern recognition in remotely sensed images. Preliminary experiments are reported that compare neural networks with a recently introduced variant known as morphological networks. A novel network node is then presented that is particularly suited to the problem of pattern recognition in multi-spectral data sets. More specifically, the node can exploit both spectral and spatial information, and implements both feature extraction and classification components of a typical image processing pipeline. Once trained, the network can be applied to large image data sets, for at the sensor to extract features of interest with two orders of magnitude speed-up compared to software implementations.
Original language | English (US) |
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Title of host publication | Proceedings - 3rd NASA/DoD Workshop on Evolvable Hardware, EH 2001 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 261-270 |
Number of pages | 10 |
Volume | 2001-January |
ISBN (Electronic) | 0769511805 |
DOIs | |
State | Published - 2001 |
Externally published | Yes |
Event | 3rd NASA/DoD Workshop on Evolvable Hardware, EH 2001 - Long Beach, United States Duration: Jul 12 2001 → Jul 14 2001 |
Other
Other | 3rd NASA/DoD Workshop on Evolvable Hardware, EH 2001 |
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Country | United States |
City | Long Beach |
Period | 7/12/01 → 7/14/01 |
ASJC Scopus subject areas
- Engineering(all)