TY - GEN
T1 - Evolving network architectures with custom computers for multi-spectral feature identification
AU - Porter, R.
AU - Gokhale, M.
AU - Harvey, N.
AU - Perkins, S.
AU - Young, C.
N1 - Publisher Copyright:
© 2001 IEEE.
PY - 2001
Y1 - 2001
N2 - This paper investigates the design of evolvable FPGA circuits where the design space is severely constrained to an interconnected network of meaningful high-level operators. The specific design domain is image processing, especially pattern recognition in remotely sensed images. Preliminary experiments are reported that compare neural networks with a recently introduced variant known as morphological networks. A novel network node is then presented that is particularly suited to the problem of pattern recognition in multi-spectral data sets. More specifically, the node can exploit both spectral and spatial information, and implements both feature extraction and classification components of a typical image processing pipeline. Once trained, the network can be applied to large image data sets, for at the sensor to extract features of interest with two orders of magnitude speed-up compared to software implementations.
AB - This paper investigates the design of evolvable FPGA circuits where the design space is severely constrained to an interconnected network of meaningful high-level operators. The specific design domain is image processing, especially pattern recognition in remotely sensed images. Preliminary experiments are reported that compare neural networks with a recently introduced variant known as morphological networks. A novel network node is then presented that is particularly suited to the problem of pattern recognition in multi-spectral data sets. More specifically, the node can exploit both spectral and spatial information, and implements both feature extraction and classification components of a typical image processing pipeline. Once trained, the network can be applied to large image data sets, for at the sensor to extract features of interest with two orders of magnitude speed-up compared to software implementations.
UR - http://www.scopus.com/inward/record.url?scp=84952933473&partnerID=8YFLogxK
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U2 - 10.1109/EH.2001.937970
DO - 10.1109/EH.2001.937970
M3 - Conference contribution
AN - SCOPUS:84952933473
T3 - Proceedings - NASA/DoD Conference on Evolvable Hardware, EH
SP - 261
EP - 270
BT - Proceedings - 3rd NASA/DoD Workshop on Evolvable Hardware, EH 2001
A2 - Zebulum, Ricardo Salem
A2 - Lohn, Jason
A2 - Stoica, Adrian
A2 - Keymeulen, Didier
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 3rd NASA/DoD Workshop on Evolvable Hardware, EH 2001
Y2 - 12 July 2001 through 14 July 2001
ER -