Evidence of Interface Trap Build-Up in Irradiated 14-nm Bulk FinFET Technologies

A. Privat, H. J. Barnaby, M. Spear, M. Esposito, J. E. Manuel, L. Clark, J. Brunhaver, A. Duvnjak, R. Jokai, K. E. Holbert, M. L. McLain, M. J. Marinella, M. P. King

Research output: Contribution to journalArticlepeer-review

Abstract

Total ionizing dose response of 14-nm bulk-Si FinFETs has been studied with a specially designed test chip. The radiation testing shows evidence of interface trap build-up on 14-nm Bulk FinFET technologies. These defects created in the isolation layer give rise to a new radiation-induced leakage path which might lead to a reliability issue in CMOS technologies at or below the 14-nm node. TCAD simulations are performed and an analytical model for TID-induced leakage current is presented to support analysis of the identified TID mechanism. TCAD simulation and analytical model results are consistent with the experimental data.

Original languageEnglish (US)
Article number9374449
Pages (from-to)671-676
Number of pages6
JournalIEEE Transactions on Nuclear Science
Volume68
Issue number5
DOIs
StatePublished - May 2021
Externally publishedYes

Keywords

  • 14-nm bulk technology
  • FinFET
  • TCAD
  • device modeling
  • interface traps
  • leakage current
  • total ionizing dose

ASJC Scopus subject areas

  • Nuclear and High Energy Physics
  • Nuclear Energy and Engineering
  • Electrical and Electronic Engineering

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