Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits

Xiaoming Chen, Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang

Research output: Contribution to journalArticle

Abstract

Random telegraph noise (RTN) has become an important reliability issue in nanoscale circuits recently. This study proposes a simulation framework to evaluate the temporal performance of digital circuits under the impact of RTN at 16 nm technology node. Two fast algorithms with linear time complexity are proposed: statistical critical path analysis and normal distribution-based analysis.The simulation results reveal that the circuit delay degradation and variation induced by RTN are both >20% and the maximum degradation and variation can be >30%. The effect of power supply tuning and gate sizing techniques on mitigating RTN is also investigated.

Original languageEnglish (US)
Pages (from-to)273-282
Number of pages10
JournalIET Circuits, Devices and Systems
Volume7
Issue number5
DOIs
StatePublished - 2013

Fingerprint

Telegraph
Digital circuits
Degradation
Critical path analysis
Delay circuits
Normal distribution
Tuning
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Control and Systems Engineering

Cite this

Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits. / Chen, Xiaoming; Luo, Hong; Wang, Yu; Cao, Yu; Xie, Yuan; Ma, Yuchun; Yang, Huazhong.

In: IET Circuits, Devices and Systems, Vol. 7, No. 5, 2013, p. 273-282.

Research output: Contribution to journalArticle

Chen, Xiaoming ; Luo, Hong ; Wang, Yu ; Cao, Yu ; Xie, Yuan ; Ma, Yuchun ; Yang, Huazhong. / Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits. In: IET Circuits, Devices and Systems. 2013 ; Vol. 7, No. 5. pp. 273-282.
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