Estimation of signal arrival times in the presence of delay noise

Sarvesh Bhardwaj, Sarma Vrudhula, David Blaauw

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Delay due to capacitive coupling of interconnects has become an important reliability issue in the design of nanometer circuits. In this paper we present a probabilistic approach towards analyzing the impact of capacitive coupling noise on signal delay. The variation in the delay is due to the variation in the relative arrival times of the aggressors and the victim. We derive expressions for the moments of the victim voltage in the presence of noise. From these we compute estimates of the earliest and latest possible arrival times of the victim. We compare the analytical results with Monte Carlo simulations using SPICE. Even though the analytical calculations are 200 times faster than the Monte Carlo simulations, the differences in the estimates of the mean and standard deviation of the arrival time is no more than 2.8%. In addition, the width of the timing intervals using the proposed approach is reduced by as much as 48% with a confidence level of 0.984. That is 98.4% of the Monte Carlo simulations result in an arrival time that falls within the derived interval which is 48% shorter.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Pages418-422
Number of pages5
DOIs
StatePublished - 2002
EventIEEE/ACM International Conference on Computer Aided Design (ICCAD) - San Jose, CA, United States
Duration: Nov 10 2002Nov 14 2002

Other

OtherIEEE/ACM International Conference on Computer Aided Design (ICCAD)
CountryUnited States
CitySan Jose, CA
Period11/10/0211/14/02

Fingerprint

SPICE
Networks (circuits)
Electric potential
Monte Carlo simulation

ASJC Scopus subject areas

  • Software

Cite this

Bhardwaj, S., Vrudhula, S., & Blaauw, D. (2002). Estimation of signal arrival times in the presence of delay noise. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (pp. 418-422) https://doi.org/10.1145/774572.774634

Estimation of signal arrival times in the presence of delay noise. / Bhardwaj, Sarvesh; Vrudhula, Sarma; Blaauw, David.

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. 2002. p. 418-422.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Bhardwaj, S, Vrudhula, S & Blaauw, D 2002, Estimation of signal arrival times in the presence of delay noise. in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. pp. 418-422, IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Jose, CA, United States, 11/10/02. https://doi.org/10.1145/774572.774634
Bhardwaj S, Vrudhula S, Blaauw D. Estimation of signal arrival times in the presence of delay noise. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. 2002. p. 418-422 https://doi.org/10.1145/774572.774634
Bhardwaj, Sarvesh ; Vrudhula, Sarma ; Blaauw, David. / Estimation of signal arrival times in the presence of delay noise. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. 2002. pp. 418-422
@inproceedings{5ac0457fbee245fdab5881e83b315cd0,
title = "Estimation of signal arrival times in the presence of delay noise",
abstract = "Delay due to capacitive coupling of interconnects has become an important reliability issue in the design of nanometer circuits. In this paper we present a probabilistic approach towards analyzing the impact of capacitive coupling noise on signal delay. The variation in the delay is due to the variation in the relative arrival times of the aggressors and the victim. We derive expressions for the moments of the victim voltage in the presence of noise. From these we compute estimates of the earliest and latest possible arrival times of the victim. We compare the analytical results with Monte Carlo simulations using SPICE. Even though the analytical calculations are 200 times faster than the Monte Carlo simulations, the differences in the estimates of the mean and standard deviation of the arrival time is no more than 2.8{\%}. In addition, the width of the timing intervals using the proposed approach is reduced by as much as 48{\%} with a confidence level of 0.984. That is 98.4{\%} of the Monte Carlo simulations result in an arrival time that falls within the derived interval which is 48{\%} shorter.",
author = "Sarvesh Bhardwaj and Sarma Vrudhula and David Blaauw",
year = "2002",
doi = "10.1145/774572.774634",
language = "English (US)",
pages = "418--422",
booktitle = "IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers",

}

TY - GEN

T1 - Estimation of signal arrival times in the presence of delay noise

AU - Bhardwaj, Sarvesh

AU - Vrudhula, Sarma

AU - Blaauw, David

PY - 2002

Y1 - 2002

N2 - Delay due to capacitive coupling of interconnects has become an important reliability issue in the design of nanometer circuits. In this paper we present a probabilistic approach towards analyzing the impact of capacitive coupling noise on signal delay. The variation in the delay is due to the variation in the relative arrival times of the aggressors and the victim. We derive expressions for the moments of the victim voltage in the presence of noise. From these we compute estimates of the earliest and latest possible arrival times of the victim. We compare the analytical results with Monte Carlo simulations using SPICE. Even though the analytical calculations are 200 times faster than the Monte Carlo simulations, the differences in the estimates of the mean and standard deviation of the arrival time is no more than 2.8%. In addition, the width of the timing intervals using the proposed approach is reduced by as much as 48% with a confidence level of 0.984. That is 98.4% of the Monte Carlo simulations result in an arrival time that falls within the derived interval which is 48% shorter.

AB - Delay due to capacitive coupling of interconnects has become an important reliability issue in the design of nanometer circuits. In this paper we present a probabilistic approach towards analyzing the impact of capacitive coupling noise on signal delay. The variation in the delay is due to the variation in the relative arrival times of the aggressors and the victim. We derive expressions for the moments of the victim voltage in the presence of noise. From these we compute estimates of the earliest and latest possible arrival times of the victim. We compare the analytical results with Monte Carlo simulations using SPICE. Even though the analytical calculations are 200 times faster than the Monte Carlo simulations, the differences in the estimates of the mean and standard deviation of the arrival time is no more than 2.8%. In addition, the width of the timing intervals using the proposed approach is reduced by as much as 48% with a confidence level of 0.984. That is 98.4% of the Monte Carlo simulations result in an arrival time that falls within the derived interval which is 48% shorter.

UR - http://www.scopus.com/inward/record.url?scp=0036907311&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036907311&partnerID=8YFLogxK

U2 - 10.1145/774572.774634

DO - 10.1145/774572.774634

M3 - Conference contribution

AN - SCOPUS:0036907311

SP - 418

EP - 422

BT - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

ER -