Enhancing the reliability of STT-RAM through circuit and system level techniques

Spin torque transfer random access memory (STT-RAM) is a promising memory technology because of its fast read access, high storage density, and very low standby power. These memories have reliability issues that need to be better understood before they can be adopted as a mainstream memory technology. In this paper, we first study the causes of errors for a single STT memory cell. We see that process variations and variations in the device geometry affect their failure rate and develop error models to capture these effects. Next we propose a joint technique based on tuning of circuit level parameters and error control coding (ECC) to achieve very high reliability. Such a combination allows the use of weaker ECC with smaller overhead. For instance, we show that by applying voltage boosting and write pulse width adjustment, the error correction capability (t) of ECC can be reduced from t=11 to t=3 to achieve a block failure rate (BFR) of 10^-9.