Enhancing the reliability of STT-RAM through circuit and system level techniques

Yunus Emre, Chengen Yang, Ketul Sutaria, Yu Cao, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

22 Citations (Scopus)

Abstract

Spin torque transfer random access memory (STT-RAM) is a promising memory technology because of its fast read access, high storage density, and very low standby power. These memories have reliability issues that need to be better understood before they can be adopted as a mainstream memory technology. In this paper, we first study the causes of errors for a single STT memory cell. We see that process variations and variations in the device geometry affect their failure rate and develop error models to capture these effects. Next we propose a joint technique based on tuning of circuit level parameters and error control coding (ECC) to achieve very high reliability. Such a combination allows the use of weaker ECC with smaller overhead. For instance, we show that by applying voltage boosting and write pulse width adjustment, the error correction capability (t) of ECC can be reduced from t=11 to t=3 to achieve a block failure rate (BFR) of 10-9.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Pages125-130
Number of pages6
DOIs
StatePublished - 2012
Event2012 IEEE Workshop on Signal Processing Systems, SiPS 2012 - Quebec City, QC, Canada
Duration: Oct 17 2012Oct 19 2012

Other

Other2012 IEEE Workshop on Signal Processing Systems, SiPS 2012
CountryCanada
CityQuebec City, QC
Period10/17/1210/19/12

Fingerprint

Random Access
Torque
Computer systems
Error Control
Data storage equipment
Networks (circuits)
Coding
Failure Rate
Process Variation
Error Model
Error correction
Error Correction
Boosting
Tuning
Adjustment
Voltage
Geometry
Cell
Electric potential

Keywords

  • Bit error rate
  • Circuit level techniques
  • Error control coding
  • Process variation
  • Spin torque transfer RAM (STT-RAM)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture

Cite this

Emre, Y., Yang, C., Sutaria, K., Cao, Y., & Chakrabarti, C. (2012). Enhancing the reliability of STT-RAM through circuit and system level techniques. In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation (pp. 125-130). [6363194] https://doi.org/10.1109/SiPS.2012.11

Enhancing the reliability of STT-RAM through circuit and system level techniques. / Emre, Yunus; Yang, Chengen; Sutaria, Ketul; Cao, Yu; Chakrabarti, Chaitali.

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. 2012. p. 125-130 6363194.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Emre, Y, Yang, C, Sutaria, K, Cao, Y & Chakrabarti, C 2012, Enhancing the reliability of STT-RAM through circuit and system level techniques. in IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation., 6363194, pp. 125-130, 2012 IEEE Workshop on Signal Processing Systems, SiPS 2012, Quebec City, QC, Canada, 10/17/12. https://doi.org/10.1109/SiPS.2012.11
Emre Y, Yang C, Sutaria K, Cao Y, Chakrabarti C. Enhancing the reliability of STT-RAM through circuit and system level techniques. In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. 2012. p. 125-130. 6363194 https://doi.org/10.1109/SiPS.2012.11
Emre, Yunus ; Yang, Chengen ; Sutaria, Ketul ; Cao, Yu ; Chakrabarti, Chaitali. / Enhancing the reliability of STT-RAM through circuit and system level techniques. IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. 2012. pp. 125-130
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