Enhancement Source-Coupled Logic for Mixed-Mode VLSI Circuits

M. Maleki; S. Kiaei

doi:10.1109/82.145301

Enhancement Source-Coupled Logic for Mixed-Mode VLSI Circuits

M. Maleki, S. Kiaei

Research output: Contribution to journal › Article › peer-review

13 Scopus citations

Abstract

Low noise enhancement source-coupled logic (ESCL) is proposed for applications in high-precision mixed-mode integrated circuits. The differential ESCL topology offers potential low-power supply noise advantages over conventional CMOS logic for mixed-mode IC’s by steering a constant current to perform the logic operation and it requires a smaller logic swing (ΔV_L < 0.2 V_dd) compared to static CMOS logic (ΔV = V_dd). For mixed-mode integrated circuits, ESCL reduces the digital switching noise by approximately two orders of magnitude (20–30 μA/gate) compared to conventional static logic spikes (0.5-1 mA/gate) which is essential to the development of sensitive on-chip analog circuitry. Results from several ESCL circuits implemented in a 2-μm p-well technology are presented.

Original language	English (US)
Pages (from-to)	399-402
Number of pages	4
Journal	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume	39
Issue number	6
DOIs	https://doi.org/10.1109/82.145301
State	Published - Jun 1992
Externally published	Yes

ASJC Scopus subject areas

Signal Processing
Electrical and Electronic Engineering

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abstract = "Low noise enhancement source-coupled logic (ESCL) is proposed for applications in high-precision mixed-mode integrated circuits. The differential ESCL topology offers potential low-power supply noise advantages over conventional CMOS logic for mixed-mode IC{\textquoteright}s by steering a constant current to perform the logic operation and it requires a smaller logic swing (ΔVL < 0.2 Vdd) compared to static CMOS logic (ΔV = Vdd). For mixed-mode integrated circuits, ESCL reduces the digital switching noise by approximately two orders of magnitude (20–30 μA/gate) compared to conventional static logic spikes (0.5-1 mA/gate) which is essential to the development of sensitive on-chip analog circuitry. Results from several ESCL circuits implemented in a 2-μm p-well technology are presented.",

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AB - Low noise enhancement source-coupled logic (ESCL) is proposed for applications in high-precision mixed-mode integrated circuits. The differential ESCL topology offers potential low-power supply noise advantages over conventional CMOS logic for mixed-mode IC’s by steering a constant current to perform the logic operation and it requires a smaller logic swing (ΔVL < 0.2 Vdd) compared to static CMOS logic (ΔV = Vdd). For mixed-mode integrated circuits, ESCL reduces the digital switching noise by approximately two orders of magnitude (20–30 μA/gate) compared to conventional static logic spikes (0.5-1 mA/gate) which is essential to the development of sensitive on-chip analog circuitry. Results from several ESCL circuits implemented in a 2-μm p-well technology are presented.

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Enhancement Source-Coupled Logic for Mixed-Mode VLSI Circuits

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