Low noise enhancement source-coupled logic (ESCL) is proposed for applications in high-precision mixed-mode integrated circuits. The differential ESCL topology offers potential low-power supply noise advantages over conventional CMOS logic for mixed-mode IC’s by steering a constant current to perform the logic operation and it requires a smaller logic swing (ΔVL < 0.2 Vdd) compared to static CMOS logic (ΔV = Vdd). For mixed-mode integrated circuits, ESCL reduces the digital switching noise by approximately two orders of magnitude (20–30 μA/gate) compared to conventional static logic spikes (0.5-1 mA/gate) which is essential to the development of sensitive on-chip analog circuitry. Results from several ESCL circuits implemented in a 2-μm p-well technology are presented.
|Original language||English (US)|
|Number of pages||4|
|Journal||IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing|
|State||Published - Jun 1992|
ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering