Enhancement source-coupled logic for mixed-mode VLSI circuits

M. Maleki, Sayfe Kiaei

Research output: Contribution to journalArticle

11 Citations (Scopus)

Abstract

Low-noise enhancement source-coupled logic (ESCL) is proposed for applications in high-precision mixed-mode integrated circuits (ICs). The differential ESCL topology offers potential low-power supply noise advantages over conventional CMOS logic for mixed-mode ICs by steering a constant current to perform the logic operation and it requires a smaller logic swing (ΔVL < 0.2 Vdd) compared to static CMOS logic (ΔV = Vdd). For mixed-mode ICs, ESCL reduces the digital switching noise by approximately two orders of magnitude (20-30 μA/gate) compared to conventional static logic spikes (0.5-1 mA/gate) which is essential to the development of sensitive on-chip analog circuitry. Results from several ESCL circuits implemented in a 2-μm p-well technology are presented.

Original languageEnglish (US)
Pages (from-to)399-402
Number of pages4
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume39
Issue number6
DOIs
StatePublished - Jun 1992
Externally publishedYes

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VLSI circuits
Coupled circuits
Logic circuits
Topology
Mixed signal integrated circuits

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering

Cite this

Enhancement source-coupled logic for mixed-mode VLSI circuits. / Maleki, M.; Kiaei, Sayfe.

In: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 39, No. 6, 06.1992, p. 399-402.

Research output: Contribution to journalArticle

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