Energy-guided exploration of on-chip network design for exa-scale computing

Mathematics

• Energy Efficient 100%
• Chip 78%
• Network Design 76%
• Cache 60%
• Memory Model 57%
• Design Space Exploration 45%
• Energy 41%
• Network on chip 40%
• Computing 38%
• System Architecture 35%
• Hierarchical Networks 32%
• High Performance Computing 31%
• Interconnect 30%
• Testbed 29%
• Architecture 22%
• Proximity 21%
• Trade-offs 20%
• Controller 19%
• Target 17%
• Hierarchy 16%
• Design 12%
• Performance 12%
• Vertex of a graph 11%

Engineering & Materials Science

• Network-on-chip 69%
• Data storage equipment 37%
• Testbeds 19%
• Controllers 11%