Energy-guided exploration of on-chip network design for exa-scale computing

Umit Y. Ogras, Yunus Emre, Jianping Xu, Timothy Kam, Michael Kishinevsky

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Designing energy-efficient systems under tight performance and energy constraints becomes increasingly challenging for exascale computing. In particular, interconnecting hundreds of cores, caches, integrated memory and I/O controllers in energy efficient way stands out as a new challenge. This paper proposes hierarchical on-chip networks that take the proximity advantage between the cores in smaller clusters as a promising approach toward energy-efficient high performance computing. The design trade-offs of hierarchical interconnect architectures are studied using a fast and scalable design space exploration tool for exascale systems with number of cores in the order of thousands. In particular, we consider a system with 720 processing nodes and two-level network hierarchy. By supporting both traditional cache-based memory model and scratch pad memory (SPM) model, the target system architecture proves to be a good testbed for energy-guided exploration of hierarchical networks.

Original languageEnglish (US)
Title of host publicationProceedings of the International Workshop on System Level Interconnect Prediction, SLIP'12
Pages24-31
Number of pages8
DOIs
StatePublished - Sep 26 2012
Externally publishedYes
EventInternational Workshop on System Level Interconnect Prediction, SLIP 2012 - San Francisco, CA, United States
Duration: Jun 3 2012Jun 3 2012

Publication series

NameInternational Workshop on System Level Interconnect Prediction, SLIP

Other

OtherInternational Workshop on System Level Interconnect Prediction, SLIP 2012
CountryUnited States
CitySan Francisco, CA
Period6/3/126/3/12

    Fingerprint

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Applied Mathematics

Cite this

Ogras, U. Y., Emre, Y., Xu, J., Kam, T., & Kishinevsky, M. (2012). Energy-guided exploration of on-chip network design for exa-scale computing. In Proceedings of the International Workshop on System Level Interconnect Prediction, SLIP'12 (pp. 24-31). (International Workshop on System Level Interconnect Prediction, SLIP). https://doi.org/10.1145/2347655.2347669