TY - GEN
T1 - Energy-guided exploration of on-chip network design for exa-scale computing
AU - Ogras, Umit Y.
AU - Emre, Yunus
AU - Xu, Jianping
AU - Kam, Timothy
AU - Kishinevsky, Michael
PY - 2012
Y1 - 2012
N2 - Designing energy-efficient systems under tight performance and energy constraints becomes increasingly challenging for exascale computing. In particular, interconnecting hundreds of cores, caches, integrated memory and I/O controllers in energy efficient way stands out as a new challenge. This paper proposes hierarchical on-chip networks that take the proximity advantage between the cores in smaller clusters as a promising approach toward energy-efficient high performance computing. The design trade-offs of hierarchical interconnect architectures are studied using a fast and scalable design space exploration tool for exascale systems with number of cores in the order of thousands. In particular, we consider a system with 720 processing nodes and two-level network hierarchy. By supporting both traditional cache-based memory model and scratch pad memory (SPM) model, the target system architecture proves to be a good testbed for energy-guided exploration of hierarchical networks.
AB - Designing energy-efficient systems under tight performance and energy constraints becomes increasingly challenging for exascale computing. In particular, interconnecting hundreds of cores, caches, integrated memory and I/O controllers in energy efficient way stands out as a new challenge. This paper proposes hierarchical on-chip networks that take the proximity advantage between the cores in smaller clusters as a promising approach toward energy-efficient high performance computing. The design trade-offs of hierarchical interconnect architectures are studied using a fast and scalable design space exploration tool for exascale systems with number of cores in the order of thousands. In particular, we consider a system with 720 processing nodes and two-level network hierarchy. By supporting both traditional cache-based memory model and scratch pad memory (SPM) model, the target system architecture proves to be a good testbed for energy-guided exploration of hierarchical networks.
UR - http://www.scopus.com/inward/record.url?scp=84866510055&partnerID=8YFLogxK
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U2 - 10.1145/2347655.2347669
DO - 10.1145/2347655.2347669
M3 - Conference contribution
AN - SCOPUS:84866510055
SN - 9781450314374
T3 - International Workshop on System Level Interconnect Prediction, SLIP
SP - 24
EP - 31
BT - Proceedings of the International Workshop on System Level Interconnect Prediction, SLIP'12
T2 - International Workshop on System Level Interconnect Prediction, SLIP 2012
Y2 - 3 June 2012 through 3 June 2012
ER -