Energy efficient mapping and voltage islanding for regular NoC under design constraints

Pavel Ghosh, Arunabha Sen

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

Computational energy consumption of the processing elements (PEs) of a NoC can be significantly reduced by scaling down their voltage levels. This creates clusters of adjacent PEs operating at the same voltage level, known as voltage islands. Excessive number of voltage islands is undesirable from the physical design perspective and due to the overhead of level shifter energy consumption between adjacent voltage islands. Considering these issues during mapping of the PEs to the NoC routers, can potentially lead to acceptable solutions with reduced overall energy consumption. In this paper, we formulate the mapping problem as an optimisation problem. We present both optimal solution, obtained by solving a mixed integer linear program (MILP), and heuristic solution based on random greedy selection. Experimental results using benchmark and real applications show that the heuristic finds near-optimal solution in almost all cases in a very small fraction of the time required to achieve the optimal solution.

Original languageEnglish (US)
Pages (from-to)132-144
Number of pages13
JournalInternational Journal of High Performance Systems Architecture
Volume2
Issue number3-4
DOIs
StatePublished - Aug 2010

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Electric potential
Energy utilization
Processing
Routers
Network-on-chip

Keywords

  • Energy efficient mapping
  • Greedy heuristic
  • MILP
  • Mixed integer linear programming
  • Network-on-chip
  • NoC
  • Randominisation
  • SoC
  • System-on-chip
  • Voltage islanding

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Energy efficient mapping and voltage islanding for regular NoC under design constraints. / Ghosh, Pavel; Sen, Arunabha.

In: International Journal of High Performance Systems Architecture, Vol. 2, No. 3-4, 08.2010, p. 132-144.

Research output: Contribution to journalArticle

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