Energy efficient in-memory binary deep neural network accelerator with dual-mode SOT-MRAM

Deliang Fan, Shaahin Angizi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Scopus citations

Abstract

In this paper, we explore potentials of leveraging spin-based in-memory computing platform as an accelerator for Binary Convolutional Neural Networks (BCNN). Such platform can implement the dominant convolution computation based on presented Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array. The proposed array architecture could simultaneously work as non-volatile memory and a reconfigurable in-memory logic (AND, OR) without add-on logic circuits to memory chip as in conventional logic-in-memory designs. The computed logic output could be also simply read out like a normal MRAM bit-cell using the shared memory peripheral circuits. We employ such intrinsic in-memory computing architecture to efficiently process data within memory to greatly reduce power hungry and omit long distance data communication concerning state-of-the-art BCNN hardware.

Original languageEnglish (US)
Title of host publicationProceedings - 35th IEEE International Conference on Computer Design, ICCD 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages609-612
Number of pages4
ISBN (Electronic)9781538622544
DOIs
StatePublished - Nov 22 2017
Externally publishedYes
Event35th IEEE International Conference on Computer Design, ICCD 2017 - Boston, United States
Duration: Nov 5 2017Nov 8 2017

Publication series

NameProceedings - 35th IEEE International Conference on Computer Design, ICCD 2017

Conference

Conference35th IEEE International Conference on Computer Design, ICCD 2017
CountryUnited States
CityBoston
Period11/5/1711/8/17

Keywords

  • Convolutional Neural Network
  • In-memory computing
  • SOT-MRAM

ASJC Scopus subject areas

  • Hardware and Architecture

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