Abstract
This paper presents a procedure to generate energy-efficient code for the Motorola DSP56K processor based on increasing the packing efficiency and minimizing the number of address instructions. The key features are a novel scheduling algorithm that reduces the dependencies between instructions, a register allocation algorithm that spills variables based on their packability, and an address code generation algorithm that minimizes the number of additional instructions. The size of the code generated by this procedure is on the average 45% (25%) smaller than that generated by Motorola's g56K (SPAM).
| Original language | English (US) |
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| Title of host publication | Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers |
| Place of Publication | Piscataway, NJ, United States |
| Publisher | IEEE |
| Pages | 247-249 |
| Number of pages | 3 |
| State | Published - 2000 |
| Externally published | Yes |
| Event | International Symposium on low Power Electronics and Design (ISLPED'2000) - Portacino Coast, Italy Duration: Jul 26 2000 → Jul 27 2000 |
Other
| Other | International Symposium on low Power Electronics and Design (ISLPED'2000) |
|---|---|
| City | Portacino Coast, Italy |
| Period | 7/26/00 → 7/27/00 |
ASJC Scopus subject areas
- General Engineering