Energy-efficient code generation for DSP56000 family

Sathishkumar Udayanarayanan, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper presents a procedure to generate energy-efficient code for the Motorola DSP56K processor based on increasing the packing efficiency and minimizing the number of address instructions. The key features are a novel scheduling algorithm that reduces the dependencies between instructions, a register allocation algorithm that spills variables based on their packability, and an address code generation algorithm that minimizes the number of additional instructions. The size of the code generated by this procedure is on the average 45% (25%) smaller than that generated by Motorola's g56K (SPAM).

Original languageEnglish (US)
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design
Pages247-249
Number of pages3
StatePublished - 2000
Externally publishedYes
EventProceedings of the 2000 Symposium on Low Power Electronics and Design ISLPED'00 - Portacino Coast, Italy
Duration: Jul 26 2000Jul 27 2000

Other

OtherProceedings of the 2000 Symposium on Low Power Electronics and Design ISLPED'00
CityPortacino Coast, Italy
Period7/26/007/27/00

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'Energy-efficient code generation for DSP56000 family'. Together they form a unique fingerprint.

  • Cite this

    Udayanarayanan, S., & Chakrabarti, C. (2000). Energy-efficient code generation for DSP56000 family. In Proceedings of the International Symposium on Low Power Electronics and Design (pp. 247-249)