Energy efficient application mapping to NoC processing elements operating at multiple voltage levels

Pavel Ghosh, Arunabha Sen, Alexander Hall

Research output: Chapter in Book/Report/Conference proceedingConference contribution

43 Citations (Scopus)

Abstract

An efficient technique for mapping application tasks to heterogeneous processing elements (PEs) on a Network-on-Chip (NoC) platform, operating at multiple voltage levels, is presented in this paper. The goal of the mapping is to minimize energy consumption subject to the performance constraints. Such a mapping involves solving several sub-problems. Most of the research effort in this area often address these subproblems in a sequential fashion or a subset of them. We take a unified approach to the problem without compromising the solution time and provide techniques for optimal and heuristic solutions. We prove that the voltage assignment component of the problem itself is NP-hard and is inapproximable within any constant factor. Our optimal solution utilizes a Mixed Integer Linear Program (MILP) formulation of the problem. The heuristic utilizes MILP relaxation and randomized rounding. Experimental results based on E3S benchmark applications and a few real applications show that our heuristic produces near-optimal solution in a fraction of time needed to find the optimal.

Original languageEnglish (US)
Title of host publicationProceedings - 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009
Pages80-85
Number of pages6
DOIs
StatePublished - 2009
Event2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009 - San Diego, CA, United States
Duration: May 10 2009May 13 2009

Other

Other2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009
CountryUnited States
CitySan Diego, CA
Period5/10/095/13/09

Fingerprint

Electric potential
Processing
Energy utilization
Network-on-chip

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Ghosh, P., Sen, A., & Hall, A. (2009). Energy efficient application mapping to NoC processing elements operating at multiple voltage levels. In Proceedings - 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009 (pp. 80-85). [5071448] https://doi.org/10.1109/NOCS.2009.5071448

Energy efficient application mapping to NoC processing elements operating at multiple voltage levels. / Ghosh, Pavel; Sen, Arunabha; Hall, Alexander.

Proceedings - 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009. 2009. p. 80-85 5071448.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ghosh, P, Sen, A & Hall, A 2009, Energy efficient application mapping to NoC processing elements operating at multiple voltage levels. in Proceedings - 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009., 5071448, pp. 80-85, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009, San Diego, CA, United States, 5/10/09. https://doi.org/10.1109/NOCS.2009.5071448
Ghosh P, Sen A, Hall A. Energy efficient application mapping to NoC processing elements operating at multiple voltage levels. In Proceedings - 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009. 2009. p. 80-85. 5071448 https://doi.org/10.1109/NOCS.2009.5071448
Ghosh, Pavel ; Sen, Arunabha ; Hall, Alexander. / Energy efficient application mapping to NoC processing elements operating at multiple voltage levels. Proceedings - 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009. 2009. pp. 80-85
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