Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

T. Patrick Xiao; Matthew J. Marinella; Christopher H. Bennett; Xuan Hu; Ben Feinberg; Robin Jacobs-Gedrim; Sapan Agarwal; John S. Brunhaver; Joseph S. Friedman; Jean Anne C. Incorvia

doi:10.1109/JXCDC.2019.2955016

Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

T. Patrick Xiao, Matthew J. Marinella, Christopher H. Bennett, Xuan Hu, Ben Feinberg, Robin Jacobs-Gedrim, Sapan Agarwal, John S. Brunhaver, Joseph S. Friedman, Jean Anne C. Incorvia

Research output: Contribution to journal › Article › peer-review

17 Scopus citations

Abstract

The domain-wall (DW)-magnetic tunnel junction (MTJ) device implements universal Boolean logic in a manner that is naturally compact and cascadable. However, an evaluation of the energy efficiency of this emerging technology for standard logic applications is still lacking. In this article, we use a previously developed compact model to construct and benchmark a 32-bit adder entirely from DW-MTJ devices that communicates with DW-MTJ registers. The results of this large-scale design and simulation indicate that while the energy cost of systems driven by spin-Transfer torque (STT) DW motion is significantly higher than previously predicted, the same concept using spin-orbit torque (SOT) switching benefits from an improvement in the energy per operation by multiple orders of magnitude, attaining competitive energy values relative to a comparable CMOS subprocessor component. This result clarifies the path toward practical implementations of an all-magnetic processor system.

Original language	English (US)
Article number	8910439
Pages (from-to)	188-196
Number of pages	9
Journal	IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Volume	5
Issue number	2
DOIs	https://doi.org/10.1109/JXCDC.2019.2955016
State	Published - Dec 2019

Keywords

Benchmarking
domain wall (DW)
magnetic logic
magnetic tunnel junction (MTJ)
post-CMOS logic
spintronics

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/JXCDC.2019.2955016

Cite this

Patrick Xiao, T., Marinella, M. J., Bennett, C. H., Hu, X., Feinberg, B., Jacobs-Gedrim, R., Agarwal, S., Brunhaver, J. S., Friedman, J. S., & Incorvia, J. A. C. (2019). Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 5(2), 188-196. Article 8910439. https://doi.org/10.1109/JXCDC.2019.2955016

Patrick Xiao, T, Marinella, MJ, Bennett, CH, Hu, X, Feinberg, B, Jacobs-Gedrim, R, Agarwal, S, Brunhaver, JS, Friedman, JS & Incorvia, JAC 2019, 'Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder', IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 5, no. 2, 8910439, pp. 188-196. https://doi.org/10.1109/JXCDC.2019.2955016

@article{625e6768d90349da807925a455f46750,

title = "Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder",

abstract = "The domain-wall (DW)-magnetic tunnel junction (MTJ) device implements universal Boolean logic in a manner that is naturally compact and cascadable. However, an evaluation of the energy efficiency of this emerging technology for standard logic applications is still lacking. In this article, we use a previously developed compact model to construct and benchmark a 32-bit adder entirely from DW-MTJ devices that communicates with DW-MTJ registers. The results of this large-scale design and simulation indicate that while the energy cost of systems driven by spin-Transfer torque (STT) DW motion is significantly higher than previously predicted, the same concept using spin-orbit torque (SOT) switching benefits from an improvement in the energy per operation by multiple orders of magnitude, attaining competitive energy values relative to a comparable CMOS subprocessor component. This result clarifies the path toward practical implementations of an all-magnetic processor system.",

keywords = "Benchmarking, domain wall (DW), magnetic logic, magnetic tunnel junction (MTJ), post-CMOS logic, spintronics",

author = "{Patrick Xiao}, T. and Marinella, {Matthew J.} and Bennett, {Christopher H.} and Xuan Hu and Ben Feinberg and Robin Jacobs-Gedrim and Sapan Agarwal and Brunhaver, {John S.} and Friedman, {Joseph S.} and Incorvia, {Jean Anne C.}",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.",

year = "2019",

month = dec,

doi = "10.1109/JXCDC.2019.2955016",

language = "English (US)",

volume = "5",

pages = "188--196",

journal = "IEEE Journal on Exploratory Solid-State Computational Devices and Circuits",

issn = "2329-9231",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "2",

}

TY - JOUR

T1 - Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

AU - Patrick Xiao, T.

AU - Marinella, Matthew J.

AU - Bennett, Christopher H.

AU - Hu, Xuan

AU - Feinberg, Ben

AU - Jacobs-Gedrim, Robin

AU - Agarwal, Sapan

AU - Brunhaver, John S.

AU - Friedman, Joseph S.

AU - Incorvia, Jean Anne C.

PY - 2019/12

Y1 - 2019/12

N2 - The domain-wall (DW)-magnetic tunnel junction (MTJ) device implements universal Boolean logic in a manner that is naturally compact and cascadable. However, an evaluation of the energy efficiency of this emerging technology for standard logic applications is still lacking. In this article, we use a previously developed compact model to construct and benchmark a 32-bit adder entirely from DW-MTJ devices that communicates with DW-MTJ registers. The results of this large-scale design and simulation indicate that while the energy cost of systems driven by spin-Transfer torque (STT) DW motion is significantly higher than previously predicted, the same concept using spin-orbit torque (SOT) switching benefits from an improvement in the energy per operation by multiple orders of magnitude, attaining competitive energy values relative to a comparable CMOS subprocessor component. This result clarifies the path toward practical implementations of an all-magnetic processor system.

AB - The domain-wall (DW)-magnetic tunnel junction (MTJ) device implements universal Boolean logic in a manner that is naturally compact and cascadable. However, an evaluation of the energy efficiency of this emerging technology for standard logic applications is still lacking. In this article, we use a previously developed compact model to construct and benchmark a 32-bit adder entirely from DW-MTJ devices that communicates with DW-MTJ registers. The results of this large-scale design and simulation indicate that while the energy cost of systems driven by spin-Transfer torque (STT) DW motion is significantly higher than previously predicted, the same concept using spin-orbit torque (SOT) switching benefits from an improvement in the energy per operation by multiple orders of magnitude, attaining competitive energy values relative to a comparable CMOS subprocessor component. This result clarifies the path toward practical implementations of an all-magnetic processor system.

KW - Benchmarking

KW - domain wall (DW)

KW - magnetic logic

KW - magnetic tunnel junction (MTJ)

KW - post-CMOS logic

KW - spintronics

UR - http://www.scopus.com/inward/record.url?scp=85075691285&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85075691285&partnerID=8YFLogxK

U2 - 10.1109/JXCDC.2019.2955016

DO - 10.1109/JXCDC.2019.2955016

M3 - Article

AN - SCOPUS:85075691285

SN - 2329-9231

VL - 5

SP - 188

EP - 196

JO - IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

JF - IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

IS - 2

M1 - 8910439

ER -

Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this