End-to-end testability analysis and DfT insertion for mixed-signal paths

Sule Ozev; Alex Orailoglu

doi:10.1109/ICCD.2004.1347902

End-to-end testability analysis and DfT insertion for mixed-signal paths

Sule Ozev, Alex Orailoglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Increasing system complexity and test cost demands new system-level solutions for mixed-signal systems. In this paper, we present a testability analysis and DfT insertion methodology for end-to-end mixed-signal paths. Based on behavioral models and path analysis, testability problems in the path are determined and classified in terms of their bottleneck. Possible solutions to each problem are identified. The DfT insertion problem is then formulated as a min-cost set cover problem to achieve the most cost-efficient solution. In experimental results where test point insertion is used as the DfT approach, nearly 50% reduction in the overall DfT overhead is achieved.

Original language	English (US)
Title of host publication	Proceedings - IEEE International Conference on Computer Design
Subtitle of host publication	VLSI in Computers and Processors, ICCD 2004
Pages	72-77
Number of pages	6
DOIs	https://doi.org/10.1109/ICCD.2004.1347902
State	Published - Dec 1 2004
Externally published	Yes
Event	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004 - San Jose, CA, United States Duration: Oct 11 2004 → Oct 13 2004

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN (Print)	1063-6404

Other

Other	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004
Country/Territory	United States
City	San Jose, CA
Period	10/11/04 → 10/13/04

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ICCD.2004.1347902

Cite this

Ozev, S., & Orailoglu, A. (2004). End-to-end testability analysis and DfT insertion for mixed-signal paths. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004 (pp. 72-77). (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). https://doi.org/10.1109/ICCD.2004.1347902

End-to-end testability analysis and DfT insertion for mixed-signal paths. / Ozev, Sule; Orailoglu, Alex.
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004. 2004. p. 72-77 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ozev, S & Orailoglu, A 2004, End-to-end testability analysis and DfT insertion for mixed-signal paths. in Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 72-77, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004, San Jose, CA, United States, 10/11/04. https://doi.org/10.1109/ICCD.2004.1347902

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End-to-end testability analysis and DfT insertion for mixed-signal paths

Abstract

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