End-to-end testability analysis and DfT insertion for mixed-signal paths

Sule Ozev, Alex Orailoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Increasing system complexity and test cost demands new system-level solutions for mixed-signal systems. In this paper, we present a testability analysis and DfT insertion methodology for end-to-end mixed-signal paths. Based on behavioral models and path analysis, testability problems in the path are determined and classified in terms of their bottleneck. Possible solutions to each problem are identified. The DfT insertion problem is then formulated as a min-cost set cover problem to achieve the most cost-efficient solution. In experimental results where test point insertion is used as the DfT approach, nearly 50% reduction in the overall DfT overhead is achieved.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Pages72-77
Number of pages6
DOIs
StatePublished - 2004
Externally publishedYes
EventProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004 - San Jose, CA, United States
Duration: Oct 11 2004Oct 13 2004

Other

OtherProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004
CountryUnited States
CitySan Jose, CA
Period10/11/0410/13/04

Fingerprint

Costs
Signal systems

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Ozev, S., & Orailoglu, A. (2004). End-to-end testability analysis and DfT insertion for mixed-signal paths. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 72-77) https://doi.org/10.1109/ICCD.2004.1347902

End-to-end testability analysis and DfT insertion for mixed-signal paths. / Ozev, Sule; Orailoglu, Alex.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. 2004. p. 72-77.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ozev, S & Orailoglu, A 2004, End-to-end testability analysis and DfT insertion for mixed-signal paths. in Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. pp. 72-77, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004, San Jose, CA, United States, 10/11/04. https://doi.org/10.1109/ICCD.2004.1347902
Ozev S, Orailoglu A. End-to-end testability analysis and DfT insertion for mixed-signal paths. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. 2004. p. 72-77 https://doi.org/10.1109/ICCD.2004.1347902
Ozev, Sule ; Orailoglu, Alex. / End-to-end testability analysis and DfT insertion for mixed-signal paths. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. 2004. pp. 72-77
@inproceedings{0c9d74d8b2c640078409e568a6b61eee,
title = "End-to-end testability analysis and DfT insertion for mixed-signal paths",
abstract = "Increasing system complexity and test cost demands new system-level solutions for mixed-signal systems. In this paper, we present a testability analysis and DfT insertion methodology for end-to-end mixed-signal paths. Based on behavioral models and path analysis, testability problems in the path are determined and classified in terms of their bottleneck. Possible solutions to each problem are identified. The DfT insertion problem is then formulated as a min-cost set cover problem to achieve the most cost-efficient solution. In experimental results where test point insertion is used as the DfT approach, nearly 50{\%} reduction in the overall DfT overhead is achieved.",
author = "Sule Ozev and Alex Orailoglu",
year = "2004",
doi = "10.1109/ICCD.2004.1347902",
language = "English (US)",
isbn = "0769522319",
pages = "72--77",
booktitle = "Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors",

}

TY - GEN

T1 - End-to-end testability analysis and DfT insertion for mixed-signal paths

AU - Ozev, Sule

AU - Orailoglu, Alex

PY - 2004

Y1 - 2004

N2 - Increasing system complexity and test cost demands new system-level solutions for mixed-signal systems. In this paper, we present a testability analysis and DfT insertion methodology for end-to-end mixed-signal paths. Based on behavioral models and path analysis, testability problems in the path are determined and classified in terms of their bottleneck. Possible solutions to each problem are identified. The DfT insertion problem is then formulated as a min-cost set cover problem to achieve the most cost-efficient solution. In experimental results where test point insertion is used as the DfT approach, nearly 50% reduction in the overall DfT overhead is achieved.

AB - Increasing system complexity and test cost demands new system-level solutions for mixed-signal systems. In this paper, we present a testability analysis and DfT insertion methodology for end-to-end mixed-signal paths. Based on behavioral models and path analysis, testability problems in the path are determined and classified in terms of their bottleneck. Possible solutions to each problem are identified. The DfT insertion problem is then formulated as a min-cost set cover problem to achieve the most cost-efficient solution. In experimental results where test point insertion is used as the DfT approach, nearly 50% reduction in the overall DfT overhead is achieved.

UR - http://www.scopus.com/inward/record.url?scp=17644421525&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=17644421525&partnerID=8YFLogxK

U2 - 10.1109/ICCD.2004.1347902

DO - 10.1109/ICCD.2004.1347902

M3 - Conference contribution

SN - 0769522319

SP - 72

EP - 77

BT - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

ER -