1 Scopus citations


Resonant clock distribution with distributed LC oscillators is promising to reducing clock power and jitter noise. Yet the difficulty in the integration of on-chip inductors still limits its application in practice. This paper resolves such a key issue with sub-50 μm magnetic inductors, which are fully compatible with the CMOS process. These inductors leverage soft magnetic coils to achieve inductances up to 4nH, Q-factor of 3 at 1 GHz with a device diameter of only 30-50 μm, resulting in area savings of nearly 100X as compared to conventional design. The latency and noise performance of the resonant clock network is demonstrated to be comparable to those using conventional inductors without soft magnetic materials. In addition, inductors with integrated magnetic materials significantly reduce mutual coupling and eddy current loss in the power grid below the clock network. These design advantages enable high density of on-chip distributed oscillators, providing better phase averaging, lower power and superior noise characteristics as compared to traditional buffer-tree based clock network.

Original languageEnglish (US)
Title of host publication2009 IEEE International Conference on Computer Design, ICCD 2009
Number of pages6
StatePublished - 2009
Event2009 IEEE International Conference on Computer Design, ICCD 2009 - Lake Tahoe, CA, United States
Duration: Oct 4 2009Oct 7 2009

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN (Print)1063-6404


Other2009 IEEE International Conference on Computer Design, ICCD 2009
CountryUnited States
CityLake Tahoe, CA

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Enabling resonant clock distribution with scaled on-chip magnetic inductors'. Together they form a unique fingerprint.

Cite this