The IEEE family of standards referred to as Time Sensitive Networking (TSN) is gaining popularity in many real-time embedded applications, including industrial automation and automotive. Based on a synchronized clock at the network layer, the TSN standards aim at deterministic behavior of message communication over an Ethernet. However, the data access time between a CPU and its network interface may be affected by the contention for shared resources and buses at each node. Any jitter on this final segment of the communication path can have a negative impact on clock synchronization and network message transmission. In this paper, we investigate the potential performance impacts to real-time TSN Ethernet caused by the level of precision to which the network clock and the CPU clock is synchronized as well as the magnitude of transmission jitter under various load conditions. Specifically, we look into the emerging architecture features in x86 systems that are considered to be commercial-off-the-shelf (COTS) platforms for embedded applications. We show that the latest generation of COTS hardware significantly reduces the jitters of clock synchronization between the software visible clock and the network, as well as reducing the jitter from when software attempts to transmit an Ethernet frame to when it actually appears on the wire. As a consequence, a significant performance improvement for software applications utilizing real-time TSN Ethernet can be attained in the emerging COTS systems.