Abstract
Coarse-Grained Reconfigurable Array (CGRA) processors accelerate inner loops of applications by exploiting instructionlevel parallelism (ILP) and in some cases also data-level and task-level parallelism (DLP & TLP). The aim of this tutorial is to give insight in CGRA architectures and their compilation techniques to exploit parallelism. These topics will be covered: • Polymorphic pipeline arrays, expanding coarse-grained arrays beyond innermost loops (Scott Mahlke, University of Michigan) • Code-generation for coarse-grained arrays: flexibility and programmer productivity (Bjorn De Sutter, Ghent University) • Memory-aware compilation techniques for CGRAs (Aviral Shrivastava, Arizona State University) • Retargetable Mapping of Loop Programs on Coarse-grained Reconfigurable Arrays (Frank Hannig, University of Erlangen-Nuremberg)
| Original language | English (US) |
|---|---|
| Title of host publication | 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010 |
| Pages | 185-186 |
| Number of pages | 2 |
| State | Published - 2010 |
| Event | 8th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2010 - Scottsdale, AZ, United States Duration: Oct 24 2010 → Oct 29 2010 |
Other
| Other | 8th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2010 |
|---|---|
| Country/Territory | United States |
| City | Scottsdale, AZ |
| Period | 10/24/10 → 10/29/10 |
Keywords
- Design
- Performance
ASJC Scopus subject areas
- Hardware and Architecture
- Software
- Electrical and Electronic Engineering