Embedded tutorial - Compilation techniques for CGRAs

Exploring all parallelization approaches

Tom Vander Aa, Praveen Raghavan, Scott Mahlke, Bjorn De Sutter, Aviral Shrivastava, Frank Hannig

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Coarse-Grained Reconfigurable Array (CGRA) processors accelerate inner loops of applications by exploiting instructionlevel parallelism (ILP) and in some cases also data-level and task-level parallelism (DLP & TLP). The aim of this tutorial is to give insight in CGRA architectures and their compilation techniques to exploit parallelism. These topics will be covered: • Polymorphic pipeline arrays, expanding coarse-grained arrays beyond innermost loops (Scott Mahlke, University of Michigan) • Code-generation for coarse-grained arrays: flexibility and programmer productivity (Bjorn De Sutter, Ghent University) • Memory-aware compilation techniques for CGRAs (Aviral Shrivastava, Arizona State University) • Retargetable Mapping of Loop Programs on Coarse-grained Reconfigurable Arrays (Frank Hannig, University of Erlangen-Nuremberg)

Original languageEnglish (US)
Title of host publication2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010
Pages185-186
Number of pages2
StatePublished - 2010
Event8th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2010 - Scottsdale, AZ, United States
Duration: Oct 24 2010Oct 29 2010

Other

Other8th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2010
CountryUnited States
CityScottsdale, AZ
Period10/24/1010/29/10

Fingerprint

Parallel processing systems
Pipelines
Productivity
Data storage equipment
Code generation

Keywords

  • Design
  • Performance

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Cite this

Vander Aa, T., Raghavan, P., Mahlke, S., De Sutter, B., Shrivastava, A., & Hannig, F. (2010). Embedded tutorial - Compilation techniques for CGRAs: Exploring all parallelization approaches. In 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010 (pp. 185-186). [5751499]

Embedded tutorial - Compilation techniques for CGRAs : Exploring all parallelization approaches. / Vander Aa, Tom; Raghavan, Praveen; Mahlke, Scott; De Sutter, Bjorn; Shrivastava, Aviral; Hannig, Frank.

2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010. 2010. p. 185-186 5751499.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Vander Aa, T, Raghavan, P, Mahlke, S, De Sutter, B, Shrivastava, A & Hannig, F 2010, Embedded tutorial - Compilation techniques for CGRAs: Exploring all parallelization approaches. in 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010., 5751499, pp. 185-186, 8th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2010, Scottsdale, AZ, United States, 10/24/10.
Vander Aa T, Raghavan P, Mahlke S, De Sutter B, Shrivastava A, Hannig F. Embedded tutorial - Compilation techniques for CGRAs: Exploring all parallelization approaches. In 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010. 2010. p. 185-186. 5751499
Vander Aa, Tom ; Raghavan, Praveen ; Mahlke, Scott ; De Sutter, Bjorn ; Shrivastava, Aviral ; Hannig, Frank. / Embedded tutorial - Compilation techniques for CGRAs : Exploring all parallelization approaches. 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010. 2010. pp. 185-186
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