TY - GEN
T1 - Elevating Low-Quality Silicon Wafers for High-Efficiency Silicon Heterojunction Solar Cell Applications
AU - Soeriyadi, Anastasia
AU - Weigand, William
AU - Wright, Brendan
AU - Stefani, Bruno Vicari
AU - Wright, Matthew
AU - Sen, Chandany
AU - Chen, Daniel
AU - Kim, Moonyong
AU - Holman, Zachary
AU - Hallam, Brett
PY - 2019/6
Y1 - 2019/6
N2 - We present defect-engineering approaches such as gettering and hydrogenation for silicon heterojunction structures. A method to evaluate the impact on the potential implied open circuit voltages of lifetime test structures is discussed. Lifetime analysis is performed on samples with silicon nitride passivation after defect-engineering to determine the injection level dependent bulk lifetime and dark saturation current density components. An implied open circuit voltage is predicted by assuming a dark saturation current density (J0e) appropriate for the silicon heterojunction structure while accounting for the measured bulk lifetime of the material. Agreement within 5 mV is observed for the validation samples. Subsequently, the technique is used to assess the impact of defect engineering on the potential implied open circuit voltage of a range of samples. We show that treated wafers are expected to have improvement in implied open-circuit voltages of from 706 mV to 730 mV for n-type Cz-Si, 625 mV to 723 mV for p-type Cz-Si, from 677 mV to 714 mV for p-type mc-Si, and from 657mV to 692 mV for p-type UMG silicon wafers.
AB - We present defect-engineering approaches such as gettering and hydrogenation for silicon heterojunction structures. A method to evaluate the impact on the potential implied open circuit voltages of lifetime test structures is discussed. Lifetime analysis is performed on samples with silicon nitride passivation after defect-engineering to determine the injection level dependent bulk lifetime and dark saturation current density components. An implied open circuit voltage is predicted by assuming a dark saturation current density (J0e) appropriate for the silicon heterojunction structure while accounting for the measured bulk lifetime of the material. Agreement within 5 mV is observed for the validation samples. Subsequently, the technique is used to assess the impact of defect engineering on the potential implied open circuit voltage of a range of samples. We show that treated wafers are expected to have improvement in implied open-circuit voltages of from 706 mV to 730 mV for n-type Cz-Si, 625 mV to 723 mV for p-type Cz-Si, from 677 mV to 714 mV for p-type mc-Si, and from 657mV to 692 mV for p-type UMG silicon wafers.
KW - defect-engineering
KW - gettering
KW - hydrogenation
KW - lifetime analysis
KW - silicon heterojunction
UR - http://www.scopus.com/inward/record.url?scp=85081592644&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85081592644&partnerID=8YFLogxK
U2 - 10.1109/PVSC40753.2019.8980613
DO - 10.1109/PVSC40753.2019.8980613
M3 - Conference contribution
AN - SCOPUS:85081592644
T3 - Conference Record of the IEEE Photovoltaic Specialists Conference
SP - 807
EP - 812
BT - 2019 IEEE 46th Photovoltaic Specialists Conference, PVSC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 46th IEEE Photovoltaic Specialists Conference, PVSC 2019
Y2 - 16 June 2019 through 21 June 2019
ER -