Abstract
The formation of interfacial oxide between high-k and Si creates a two-layer dielectric in the MOS structure. In this paper, we present a model to describe electrical breakdown in the two-layer dielectric. Depending on the thickness ratio of the two dielectric layers, electrical breakdown can occur either in one dielectric after the other or simultaneously. In the case of one-by-one breakdown, the current through the two-layer dielectric shows three regimes with applied voltage: tunneling through two layers, tunneling through one layer, and breakdown for both layers. Our model has been compared with experimental data obtained from the HfO x/SiO 2 MOS structure, and a good agreement is achieved. This model can be used to estimate either the thickness, breakdown field, or dielectric constant of each of the two dielectric layers. It can also predict the overall breakdown voltage for different combinations of dielectric layers. When combined with C-V measurements, more information about the two-layer dielectric is obtained.
| Original language | English (US) |
|---|---|
| Title of host publication | Materials Research Society Symposium Proceedings |
| Editors | J. Morais, D. Kumar, M. Houssa, R.K. Singh, D. Landheer, R. Ramesh, R.M. Wallace, S. Guha, H. Koinuma |
| Pages | 43-48 |
| Number of pages | 6 |
| Volume | 811 |
| State | Published - 2004 |
| Externally published | Yes |
| Event | Integration of Advanced Micro- and Nanoelectronic Devices - Critical Issues and Solutions - San Francisco, CA, United States Duration: Apr 13 2004 → Apr 16 2004 |
Other
| Other | Integration of Advanced Micro- and Nanoelectronic Devices - Critical Issues and Solutions |
|---|---|
| Country/Territory | United States |
| City | San Francisco, CA |
| Period | 4/13/04 → 4/16/04 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials