Abstract
To overcome many drawbacks in the current JPEG standard for still image compression, a new standard, JPEG2000, is under development by the International Standard Organization. Embedded bit plane coding is the heart of the JPEG2000 encoder. This encoder is more complex and has significantly higher computational requirements compared to the entropy encoding in current JPEG standard. Because of the inherent bit-wise processing of the entropy encoder in JPEG2000, memory traffic is a substantial component in software implementation. However, in hardware implementation, the lookup tables can be mapped to logic gates and memory accesses for the state bit computation can be reduced significantly by careful design. In this paper, we present an efficient VLSI architecture for embedded bit-plane coding in JPEG2000 that reduces the number of memory accesses. To better understand the interaction of this architecture with the rest of the coder, we also present a system level architecture for efficient implementation of JPEG2000 in hardware.
Original language | English (US) |
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Title of host publication | Proceedings of SPIE - The International Society for Optical Engineering |
Editors | A.G. Tescher |
Pages | 246-257 |
Number of pages | 12 |
Volume | 4472 |
DOIs | |
State | Published - 2001 |
Event | Applications for Digital Image Processing XXIV - San Diego, CA, United States Duration: Jul 31 2001 → Aug 3 2001 |
Other
Other | Applications for Digital Image Processing XXIV |
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Country/Territory | United States |
City | San Diego, CA |
Period | 7/31/01 → 8/3/01 |
Keywords
- Bit plane coding
- EBCOT architecture
- JPEG2000
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Condensed Matter Physics