Efficient simulation of parametric faults for multi-stage analog circuits

Fang Liu, Sule Ozev

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Due to process variability which makes the analog circuit response probabilistic, fault simulation effectively requires a statistical analysis for each fault. As a result, fault simulation presents the major computational time component in analog test automation. While recently a number of statistical analysis approaches for analog circuits have been proposed, overall computational time is a big concern when a high number of parametric faults need to be evaluated. We present a series of schemes to increase the efficiency of fault simulation by extracting and reusing information from one fault simulation to another. Experiments on a baseband amplifier circuit confirm that the proposed techniques can be collectively applied to provide about a 50-fold simulation time saving at the cost of less than 3% loss in accuracy when compared with similar prior techniques.

Original languageEnglish (US)
Title of host publicationProceedings - International Test Conference
DOIs
StatePublished - 2008
Externally publishedYes
Event2007 IEEE International Test Conference, ITC - Santa Clara, CA, United States
Duration: Oct 23 2007Oct 25 2007

Other

Other2007 IEEE International Test Conference, ITC
CountryUnited States
CitySanta Clara, CA
Period10/23/0710/25/07

Fingerprint

Analog circuits
Statistical methods
Automation
Networks (circuits)
Experiments

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Efficient simulation of parametric faults for multi-stage analog circuits. / Liu, Fang; Ozev, Sule.

Proceedings - International Test Conference. 2008. 4437630.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Liu, F & Ozev, S 2008, Efficient simulation of parametric faults for multi-stage analog circuits. in Proceedings - International Test Conference., 4437630, 2007 IEEE International Test Conference, ITC, Santa Clara, CA, United States, 10/23/07. https://doi.org/10.1109/TEST.2007.4437630
Liu, Fang ; Ozev, Sule. / Efficient simulation of parametric faults for multi-stage analog circuits. Proceedings - International Test Conference. 2008.
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