Efficient simulation of parametric faults for multi-stage analog circuits

Fang Liu, Sule Ozev

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Due to process variability which makes the analog circuit response probabilistic, fault simulation effectively requires a statistical analysis for each fault. As a result, fault simulation presents the major computational time component in analog test automation. While recently a number of statistical analysis approaches for analog circuits have been proposed, overall computational time is a big concern when a high number of parametric faults need to be evaluated. We present a series of schemes to increase the efficiency of fault simulation by extracting and reusing information from one fault simulation to another. Experiments on a baseband amplifier circuit confirm that the proposed techniques can be collectively applied to provide about a 50-fold simulation time saving at the cost of less than 3% loss in accuracy when compared with similar prior techniques.

Original languageEnglish (US)
Title of host publication2007 IEEE International Test Conference, ITC
DOIs
StatePublished - Mar 3 2008
Externally publishedYes
Event2007 IEEE International Test Conference, ITC - Santa Clara, CA, United States
Duration: Oct 23 2007Oct 25 2007

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539

Other

Other2007 IEEE International Test Conference, ITC
CountryUnited States
CitySanta Clara, CA
Period10/23/0710/25/07

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics

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  • Cite this

    Liu, F., & Ozev, S. (2008). Efficient simulation of parametric faults for multi-stage analog circuits. In 2007 IEEE International Test Conference, ITC [4437630] (Proceedings - International Test Conference). https://doi.org/10.1109/TEST.2007.4437630