This paper present a wide range of algorithms and architectures for computing the 1-D and 2-D discrete wavelet transform (DWT) and the 1-D and 2-D continuous wavelet transform (CWT). The algorithms and architectures presented here are independent of the size and nature of the wavelet function. New on-line algorithms are proposed for the DWT and the CWT that require significantly small storage. The proposed systolic array and the parallel filter architectures implement these on-line algorithms and are optimal both with respect to area and time (under the word-serial model). Moreover, these architectures are very regular and support single chip implementations in VLSI. The proposed SIMD architectures implement the existing pyramid and a’trous algorithms and are optimal with respect to time.
ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering