Efficient realizations of encoders and decoders based on the 2-D discrete wavelet transform

Chaitali Chakrabarti, Clint Mumford

Research output: Contribution to journalArticle

33 Citations (Scopus)

Abstract

In this paper, we present architectures and scheduling algorithms for encoders and decoders that are based on the two-dimensional discrete wavelet transform. We consider the design of encoders and decoders individually, as well as in an integrated encoder-decoder system. We propose architectures ranging from a single-instruction multiple-data processor arrays to folded architectures that are suitable for single-chip implementations. The scheduling algorithms for the folded architectures range from those that try to minimize the latency to those that try to minimize the storage and keep the data flow regular. We include a comparison of the performance of these algorithms to aid the designer in choosing one that is best suited for a specific application.

Original languageEnglish (US)
Pages (from-to)289-298
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume7
Issue number3
DOIs
StatePublished - 1999

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Discrete wavelet transforms
Scheduling algorithms
Parallel processing systems

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

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