Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints

Pavel Ghosh, Arunabha Sen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (PEs). This reduction in energy consumption comes at the cost of the energy consumption of the level shifters between voltage islands. Moreover, from physical design perspective it is desirable to have a limited number of voltage islands. Considering voltage islanding during mapping of the PEs to the NoC routers can significantly reduce both the computational and the level-shifter energy consumptions and the communication energy consumption on the NoC links. In this paper, we formulate the problem as an optimization problem with an objective of minimizing the overall energy consumption constrained by the performance in terms of delay and the maximum number of voltage islands. We provide the optimal solution to our problem using Mixed Integer Linear Program (MILP) formulation. We also propose a heuristic based on random greedy selection to solve the problem. Experimental results using E3S benchmark applications and some real applications show that the heuristic finds near-optimal solution in almost all cases in a very small fraction of the time required to achieve the optimal solution.

Original languageEnglish (US)
Title of host publicationAPPLIED COMPUTING 2010 - The 25th Annual ACM Symposium on Applied Computing
Pages535-541
Number of pages7
DOIs
StatePublished - Jul 23 2010
Event25th Annual ACM Symposium on Applied Computing, SAC 2010 - Sierre, Switzerland
Duration: Mar 22 2010Mar 26 2010

Publication series

NameProceedings of the ACM Symposium on Applied Computing

Other

Other25th Annual ACM Symposium on Applied Computing, SAC 2010
Country/TerritorySwitzerland
CitySierre
Period3/22/103/26/10

Keywords

  • greedy randomized heuristic
  • integer linear program
  • multi-processor system-on-chip (MPSoC)
  • network-on-chip (NoC)
  • voltage islanding

ASJC Scopus subject areas

  • Software

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