Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints

Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (PEs). This reduction in energy consumption comes at the cost of the energy consumption of the level shifters between voltage islands. Moreover, from physical design perspective it is desirable to have a limited number of voltage islands. Considering voltage islanding during mapping of the PEs to the NoC routers can significantly reduce both the computational and the level-shifter energy consumptions and the communication energy consumption on the NoC links. In this paper, we formulate the problem as an optimization problem with an objective of minimizing the overall energy consumption constrained by the performance in terms of delay and the maximum number of voltage islands. We provide the optimal solution to our problem using Mixed Integer Linear Program (MILP) formulation. We also propose a heuristic based on random greedy selection to solve the problem. Experimental results using E3S benchmark applications and some real applications show that the heuristic finds near-optimal solution in almost all cases in a very small fraction of the time required to achieve the optimal solution.