TY - GEN
T1 - Efficient heap data management on software managed manycore architectures
AU - Lin, Jinn Pean
AU - Lu, Jing
AU - Cai, Jian
AU - Shrivastava, Aviral
N1 - Funding Information:
This work was partially supported by funding from NIST Award 70NANB16H305, and by National Science Foundation grants, CAREER CCF-0916652, CNS 1525855, CPS 1645578, and CCF 172346 - the NSF/Intel joint research center for Computer Assisted Programming for Heterogeneous Architectures (CAPA).
Publisher Copyright:
© 2019 IEEE.
PY - 2019/5/9
Y1 - 2019/5/9
N2 - Software Managed Manycore (SMM) architectures have been proposed as a solution for scaling the memory architecture. In a typical SMM architecture, Scratch Pad Memories (SPM) are used instead of caches, and data must be explicitly managed in software. While all code and data need to be managed, heap management on SMMs is especially challenging due to the highly dynamic nature of heap data access. Existing techniques spend over 90% of execution time on heap data management, which largely compromised the power efficiency of SMM architectures. This paper presents compiler-based efficient techniques that reduce heap management overhead. Experimental results on benchmarks from MiBench [1] executing on an SMM processor modeled in Gem5 demonstrate that our approach implemented in LLVM 3.8 can improve execution time by an average of 80%, compared to the state-of-the-art [2].
AB - Software Managed Manycore (SMM) architectures have been proposed as a solution for scaling the memory architecture. In a typical SMM architecture, Scratch Pad Memories (SPM) are used instead of caches, and data must be explicitly managed in software. While all code and data need to be managed, heap management on SMMs is especially challenging due to the highly dynamic nature of heap data access. Existing techniques spend over 90% of execution time on heap data management, which largely compromised the power efficiency of SMM architectures. This paper presents compiler-based efficient techniques that reduce heap management overhead. Experimental results on benchmarks from MiBench [1] executing on an SMM processor modeled in Gem5 demonstrate that our approach implemented in LLVM 3.8 can improve execution time by an average of 80%, compared to the state-of-the-art [2].
UR - http://www.scopus.com/inward/record.url?scp=85066914338&partnerID=8YFLogxK
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U2 - 10.1109/VLSID.2019.00065
DO - 10.1109/VLSID.2019.00065
M3 - Conference contribution
AN - SCOPUS:85066914338
T3 - Proceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held concurrently with 18th International Conference on Embedded Systems, ES 2019
SP - 269
EP - 274
BT - Proceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held concurrently with 18th International Conference on Embedded Systems, ES 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 32nd International Conference on VLSI Design, VLSID 2019
Y2 - 5 January 2019 through 9 January 2019
ER -