Efficient generation of delay change curves for noise-aware static timing analysis

K. Agarwal, Yu Cao, T. Sato, D. Sylvester, Chenming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Scopus citations

Abstract

In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on any victim/aggressor configuration. Such an approach captures important noise considerations such as the possibility of delay change even when the switching windows of neighboring gates do not overlap. The technique is model-independent, which we demonstrate by using several crosstalk noise models to obtain results. Furthermore, we extend an existing noise model to more accurately handle multiple aggressors in the timing analysis framework. DCC results from the analytical approach closely match those from time-consuming SPICE simulations, making timing analysis using DCCs efficient as well as accurate.

Original languageEnglish (US)
Title of host publicationProceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages77-84
Number of pages8
ISBN (Print)0769514413, 9780769514413
DOIs
StatePublished - 2002
Externally publishedYes
Event7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 - Bangalore, India
Duration: Jan 7 2002Jan 11 2002

Other

Other7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
Country/TerritoryIndia
CityBangalore
Period1/7/021/11/02

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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