Efficient algorithms for identifying the minimum leakage states in CMOS combinational logic

Kaviraj Chopra, Sarma B K Vrudhula, Sarvesh Bhardwaj

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Power dissipation in CMOS circuits during inactive periods (static power) has become a significant part of the total power dissipation. This is particularly problematic for portable, battery powered systems, which are often in standby mode for long periods. It is well known that the major component of static power dissipation is due to subthreshold conduction. For individual gates, this leakage can vary by an order of magnitude over the gate 's input states. Consequently, one way to minimize the leakage is to drive the inputs of the circuit to a state at which the leakage is minimum. In this paper, we present a new approach to identify all minimum leakage states. The method performs implicit enumeration based on integer valued decision diagrams. Since the search space for minimum leakage vector is exponential in the number of primary inputs, the enumeration is done with respect to the minimum balanced cut of the digraph representation of the circuit. The algorithm was successfully tested on the ISCAS85 and MCNC91 benchmark circuits.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE International Conference on VLSI Design
Pages240-245
Number of pages6
Volume17
StatePublished - 2004
Externally publishedYes
EventProceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded Systems Design - Mumbai, India
Duration: Jan 5 2004Jan 9 2004

Other

OtherProceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded Systems Design
CountryIndia
CityMumbai
Period1/5/041/9/04

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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