### Abstract

The algorithm has been programmed to handle large circuits and is based on some properties of Boolean differences that make the generation of the complete test set very efficient. This algorithm can be modified so that it can be programmed on computers with small storage space. The modified algorithm can efficiently generate a subset of the complete test set of each of the faults under consideration. Some discussion is given to provide some insight into the relationship among undetectable faults, tests for detectable single faults, and circuit redundancies. Some ideas on the construction of test sets for detecting multiple faults based on Boolean differences are presented.

Original language | English (US) |
---|---|

Pages (from-to) | 1245-1251 |

Number of pages | 7 |

Journal | IEEE Transactions on Computers |

Volume | C-20 |

Issue number | 11 |

State | Published - Nov 1971 |

Externally published | Yes |

### Fingerprint

### ASJC Scopus subject areas

- Hardware and Architecture
- Electrical and Electronic Engineering

### Cite this

*IEEE Transactions on Computers*,

*C-20*(11), 1245-1251.

**Efficient algorithm for generating complete test sets for combinational logic circuits.** / Yau, Sik-Sang; TANG YS, YS.

Research output: Contribution to journal › Article

*IEEE Transactions on Computers*, vol. C-20, no. 11, pp. 1245-1251.

}

TY - JOUR

T1 - Efficient algorithm for generating complete test sets for combinational logic circuits

AU - Yau, Sik-Sang

AU - TANG YS, YS

PY - 1971/11

Y1 - 1971/11

N2 - The algorithm has been programmed to handle large circuits and is based on some properties of Boolean differences that make the generation of the complete test set very efficient. This algorithm can be modified so that it can be programmed on computers with small storage space. The modified algorithm can efficiently generate a subset of the complete test set of each of the faults under consideration. Some discussion is given to provide some insight into the relationship among undetectable faults, tests for detectable single faults, and circuit redundancies. Some ideas on the construction of test sets for detecting multiple faults based on Boolean differences are presented.

AB - The algorithm has been programmed to handle large circuits and is based on some properties of Boolean differences that make the generation of the complete test set very efficient. This algorithm can be modified so that it can be programmed on computers with small storage space. The modified algorithm can efficiently generate a subset of the complete test set of each of the faults under consideration. Some discussion is given to provide some insight into the relationship among undetectable faults, tests for detectable single faults, and circuit redundancies. Some ideas on the construction of test sets for detecting multiple faults based on Boolean differences are presented.

UR - http://www.scopus.com/inward/record.url?scp=0015161219&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0015161219&partnerID=8YFLogxK

M3 - Article

VL - C-20

SP - 1245

EP - 1251

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 11

ER -