Efficient algorithm for generating complete test sets for combinational logic circuits

Sik-Sang Yau, YS TANG YS

Research output: Contribution to journalArticle

41 Citations (Scopus)

Abstract

The algorithm has been programmed to handle large circuits and is based on some properties of Boolean differences that make the generation of the complete test set very efficient. This algorithm can be modified so that it can be programmed on computers with small storage space. The modified algorithm can efficiently generate a subset of the complete test set of each of the faults under consideration. Some discussion is given to provide some insight into the relationship among undetectable faults, tests for detectable single faults, and circuit redundancies. Some ideas on the construction of test sets for detecting multiple faults based on Boolean differences are presented.

Original languageEnglish (US)
Pages (from-to)1245-1251
Number of pages7
JournalIEEE Transactions on Computers
VolumeC-20
Issue number11
StatePublished - Nov 1971
Externally publishedYes

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Combinatorial circuits
Logic circuits
Test Set
Fault
Efficient Algorithms
Logic
Networks (circuits)
Set theory
Redundancy
Subset

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Efficient algorithm for generating complete test sets for combinational logic circuits. / Yau, Sik-Sang; TANG YS, YS.

In: IEEE Transactions on Computers, Vol. C-20, No. 11, 11.1971, p. 1245-1251.

Research output: Contribution to journalArticle

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