Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion

Yu Cao; Xuejue Huang; Norman Chang; Shen Lin; O. Sam Nakagawa; Weize Xie; Chenming Hu

doi:10.1109/ISQED.2001.915225

Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion

Yu Cao, Xuejue Huang, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Chenming Hu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

A new approach to handle the inductance effect on multiple signal lines is presented. The worst case switching pattern is first identified. Then a numerical approach is used to model the effective loop inductance (L_eff) for multiple lines. Based on look-up table for L_eff, an equivalent single line model can be generated to decouple a specific signal line from the others to perform static timing analysis. Compared to the use of full RLC netlist for multiple lines, this approach greatly improves the computation efficiency and maintains accuracy for timing and signal integrity analysis. Applications to repeater insertion in the critical path chains are demonstrated. For a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, we find that same number of repeaters is inserted for optimal delay according to both the RC and RLC multiple line models.

Original language	English (US)
Title of host publication	Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001
Publisher	IEEE Computer Society
Pages	185-190
Number of pages	6
ISBN (Electronic)	0769510256
DOIs	https://doi.org/10.1109/ISQED.2001.915225
State	Published - 2001
Externally published	Yes
Event	2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001 - San Jose, United States Duration: Mar 26 2001 → Mar 28 2001

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
Volume	2001-January
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Other

Other	2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001
Country/Territory	United States
City	San Jose
Period	3/26/01 → 3/28/01

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ISQED.2001.915225

Cite this

Cao, Y., Huang, X., Chang, N., Lin, S., Nakagawa, O. S., Xie, W., & Hu, C. (2001). Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion. In Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001 (pp. 185-190). Article 915225 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2001-January). IEEE Computer Society. https://doi.org/10.1109/ISQED.2001.915225

Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion. / Cao, Yu; Huang, Xuejue; Chang, Norman et al.
Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001. IEEE Computer Society, 2001. p. 185-190 915225 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2001-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Cao, Y, Huang, X, Chang, N, Lin, S, Nakagawa, OS, Xie, W & Hu, C 2001, Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion. in Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001., 915225, Proceedings - International Symposium on Quality Electronic Design, ISQED, vol. 2001-January, IEEE Computer Society, pp. 185-190, 2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001, San Jose, United States, 3/26/01. https://doi.org/10.1109/ISQED.2001.915225

Cao Y, Huang X, Chang N, Lin S, Nakagawa OS, Xie W et al. Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion. In Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001. IEEE Computer Society. 2001. p. 185-190. 915225. (Proceedings - International Symposium on Quality Electronic Design, ISQED). doi: 10.1109/ISQED.2001.915225

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title = "Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion",

abstract = "A new approach to handle the inductance effect on multiple signal lines is presented. The worst case switching pattern is first identified. Then a numerical approach is used to model the effective loop inductance (Leff) for multiple lines. Based on look-up table for Leff, an equivalent single line model can be generated to decouple a specific signal line from the others to perform static timing analysis. Compared to the use of full RLC netlist for multiple lines, this approach greatly improves the computation efficiency and maintains accuracy for timing and signal integrity analysis. Applications to repeater insertion in the critical path chains are demonstrated. For a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, we find that same number of repeaters is inserted for optimal delay according to both the RC and RLC multiple line models.",

author = "Yu Cao and Xuejue Huang and Norman Chang and Shen Lin and Nakagawa, {O. Sam} and Weize Xie and Chenming Hu",

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AU - Xie, Weize

AU - Hu, Chenming

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AB - A new approach to handle the inductance effect on multiple signal lines is presented. The worst case switching pattern is first identified. Then a numerical approach is used to model the effective loop inductance (Leff) for multiple lines. Based on look-up table for Leff, an equivalent single line model can be generated to decouple a specific signal line from the others to perform static timing analysis. Compared to the use of full RLC netlist for multiple lines, this approach greatly improves the computation efficiency and maintains accuracy for timing and signal integrity analysis. Applications to repeater insertion in the critical path chains are demonstrated. For a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, we find that same number of repeaters is inserted for optimal delay according to both the RC and RLC multiple line models.

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Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion

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