Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion

Yu Cao, Xuejue Huang, Norman H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu

Research output: Contribution to journalArticle

24 Scopus citations

Abstract

A new approach to handle induct effects for multiple signal lines is presented. The worst-case switching pattern is first identified. Then a numerical approach is used to model the effective loop inductance (Leff)) for multiple lines. Based on a look-up table for Leff, an equivalent single line model can be generated to decouple a specific signal line from the others to perform static timing analysis. Compared to the use of full RLC netlists for multiple lines, this approach greatly improves the computational efficiency and maintains accuracy for timing and signal integrity analysis. We apply these models to repeater insertion in critical paths and find that, for a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, we find that same number of repeaters is inserted for optimal delay according to both the RC and RLC models.

Original languageEnglish (US)
Pages (from-to)799-805
Number of pages7
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume10
Issue number6
DOIs
StatePublished - Dec 2002

Keywords

  • Delay
  • Effective loop inductance
  • Inductance
  • Interconnect
  • Repeater insertion
  • Timing analysis

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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