EDF scheduling using two-mode voltage-clock-scaling for hard real-time systems

Yann-Hang Lee, Yoonmee Doh, C. M. Krishna

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

Scaling down power supply voltage yields a quadratic reduction in dynamic power dissipation and also requires a reduction in clock frequency. In order to meet task deadlines in hard real-time systems, the delay penalty in voltage scaling needs to be carefully considered to achieve low power consumption. In this paper, we focus on dynamic reclaiming of early released resources in Earliest Deadline First (EDF) scheduling using voltage scaling. In addition to a static voltage assignment, we propose a new dynamic-mode assignment, which has a flexible voltage mode setting at run-time enabling much larger energy savings. Using simulation results and exploiting the interplay between power supply voltage, frequency, and circuit delay in CMOS technology, we find the optimal twolevel voltage settings that minimize energy consumption.

Original languageEnglish (US)
Title of host publicationCASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
PublisherAssociation for Computing Machinery, Inc
Pages221-228
Number of pages8
ISBN (Electronic)1581133995, 9781581133998
DOIs
StatePublished - Nov 16 2001
Event2nd International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2001 - Atlanta, United States
Duration: Nov 16 2001Nov 17 2001

Other

Other2nd International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2001
CountryUnited States
CityAtlanta
Period11/16/0111/17/01

Keywords

  • Dynamic reclaiming
  • Energy and power optimization
  • Real-time systems
  • Scheduling
  • Voltage scaling

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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  • Cite this

    Lee, Y-H., Doh, Y., & Krishna, C. M. (2001). EDF scheduling using two-mode voltage-clock-scaling for hard real-time systems. In CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (pp. 221-228). Association for Computing Machinery, Inc. https://doi.org/10.1145/502217.502255