EDF scheduling using two-mode voltage-clock-scaling for hard real-time systems

Yann-Hang Lee; Yoonmee Doh; C. M. Krishna

doi:10.1145/502217.502255

EDF scheduling using two-mode voltage-clock-scaling for hard real-time systems

Yann-Hang Lee, Yoonmee Doh, C. M. Krishna

IAFSE-CIDSE: Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Scopus citations

Abstract

Scaling down power supply voltage yields a quadratic reduction in dynamic power dissipation and also requires a reduction in clock frequency. In order to meet task deadlines in hard real-time systems, the delay penalty in voltage scaling needs to be carefully considered to achieve low power consumption. In this paper, we focus on dynamic reclaiming of early released resources in Earliest Deadline First (EDF) scheduling using voltage scaling. In addition to a static voltage assignment, we propose a new dynamic-mode assignment, which has a flexible voltage mode setting at run-time enabling much larger energy savings. Using simulation results and exploiting the interplay between power supply voltage, frequency, and circuit delay in CMOS technology, we find the optimal twolevel voltage settings that minimize energy consumption.

Original language	English (US)
Title of host publication	CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
Publisher	Association for Computing Machinery, Inc
Pages	221-228
Number of pages	8
ISBN (Electronic)	1581133995, 9781581133998
DOIs	https://doi.org/10.1145/502217.502255
State	Published - Nov 16 2001
Event	2nd International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2001 - Atlanta, United States Duration: Nov 16 2001 → Nov 17 2001

Other

Other	2nd International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2001
Country	United States
City	Atlanta
Period	11/16/01 → 11/17/01

Keywords

Dynamic reclaiming
Energy and power optimization
Real-time systems
Scheduling
Voltage scaling

ASJC Scopus subject areas

Hardware and Architecture
Software
Electrical and Electronic Engineering

Access to Document

10.1145/502217.502255

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EDF scheduling using two-mode voltage-clock-scaling for hard real-time systems. / Lee, Yann-Hang; Doh, Yoonmee; Krishna, C. M.

CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. Association for Computing Machinery, Inc, 2001. p. 221-228.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, Y-H, Doh, Y & Krishna, CM 2001, EDF scheduling using two-mode voltage-clock-scaling for hard real-time systems. in CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. Association for Computing Machinery, Inc, pp. 221-228, 2nd International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2001, Atlanta, United States, 11/16/01. https://doi.org/10.1145/502217.502255

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abstract = "Scaling down power supply voltage yields a quadratic reduction in dynamic power dissipation and also requires a reduction in clock frequency. In order to meet task deadlines in hard real-time systems, the delay penalty in voltage scaling needs to be carefully considered to achieve low power consumption. In this paper, we focus on dynamic reclaiming of early released resources in Earliest Deadline First (EDF) scheduling using voltage scaling. In addition to a static voltage assignment, we propose a new dynamic-mode assignment, which has a flexible voltage mode setting at run-time enabling much larger energy savings. Using simulation results and exploiting the interplay between power supply voltage, frequency, and circuit delay in CMOS technology, we find the optimal twolevel voltage settings that minimize energy consumption.",

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AB - Scaling down power supply voltage yields a quadratic reduction in dynamic power dissipation and also requires a reduction in clock frequency. In order to meet task deadlines in hard real-time systems, the delay penalty in voltage scaling needs to be carefully considered to achieve low power consumption. In this paper, we focus on dynamic reclaiming of early released resources in Earliest Deadline First (EDF) scheduling using voltage scaling. In addition to a static voltage assignment, we propose a new dynamic-mode assignment, which has a flexible voltage mode setting at run-time enabling much larger energy savings. Using simulation results and exploiting the interplay between power supply voltage, frequency, and circuit delay in CMOS technology, we find the optimal twolevel voltage settings that minimize energy consumption.

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