TY - GEN
T1 - ECG authentication neural network hardware design with collective optimization of low precision and structured compression
AU - Cherupally, Sai Kiran
AU - Srivastava, Gaurav
AU - Yin, Shihui
AU - Kadetotad, Deepak
AU - Bae, Chisung
AU - Kim, Sang Joon
AU - Jae-Sun, Seo
N1 - Funding Information:
This work is in part supported by NSF grant 1652866, Samsung Advanced Institute of Technology, and C-BRIC, one of six centers in JUMP, a SRC program sponsored by DARPA.
Publisher Copyright:
© 2019 IEEE
PY - 2019
Y1 - 2019
N2 - For wearable devices that monitor personal health, secure access to private medical data becomes a crucial feature. Nowadays, device authentication based on biometrics such as fingerprint or iris has become increasingly popular. In this work, we investigate using electrocardiogram (ECG) signals as the biometric modality for device authentication, and we present accurate and low-power ECG-based authentication hardware. Deep neural networks (DNNs) have been employed with a cost function that maximizes inter-individual distance and minimizes intra-individual distance over time. During DNN training, we also introduce joint optimization of low-precision and structured sparsity, so that the real-time authentication hardware can consume minimal energy and area. Experimental results of custom hardware designed in 65nm LP CMOS technology exhibit low power consumption of 59.4 µW for real-time ECG authentication with a low equal error rate of 1.002% for a large 741-subject in-house ECG database.
AB - For wearable devices that monitor personal health, secure access to private medical data becomes a crucial feature. Nowadays, device authentication based on biometrics such as fingerprint or iris has become increasingly popular. In this work, we investigate using electrocardiogram (ECG) signals as the biometric modality for device authentication, and we present accurate and low-power ECG-based authentication hardware. Deep neural networks (DNNs) have been employed with a cost function that maximizes inter-individual distance and minimizes intra-individual distance over time. During DNN training, we also introduce joint optimization of low-precision and structured sparsity, so that the real-time authentication hardware can consume minimal energy and area. Experimental results of custom hardware designed in 65nm LP CMOS technology exhibit low power consumption of 59.4 µW for real-time ECG authentication with a low equal error rate of 1.002% for a large 741-subject in-house ECG database.
KW - Authentication
KW - Deep neural network
KW - ECG
KW - Low-power hardware
KW - Structural sparsity
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U2 - 10.1109/ISCAS.2019.8702308
DO - 10.1109/ISCAS.2019.8702308
M3 - Conference contribution
AN - SCOPUS:85066794346
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
Y2 - 26 May 2019 through 29 May 2019
ER -