TY - GEN
T1 - Dynamic test scheduling for analog circuits for improved test quality
AU - Yilmaz, Ender
AU - Ozev, Sule
PY - 2008/12/1
Y1 - 2008/12/1
N2 - In this paper, we present an innovative test scheduling method to improve test quality and/or reduce test time for analog circuits. Our dynamic test scheduling approach predicts the fail probability of unmeasured specifications with the aim of passing statistically well-behaved chips early on so as to devote more resources to marginal devices. Results show that for a gain controlled LNA circuit, with 48 specification parameters, it is possible to achieve 67% improvement in test quality for the same test time or 19.2% test time reduction with the same test quality compared to the widely used set cover method.
AB - In this paper, we present an innovative test scheduling method to improve test quality and/or reduce test time for analog circuits. Our dynamic test scheduling approach predicts the fail probability of unmeasured specifications with the aim of passing statistically well-behaved chips early on so as to devote more resources to marginal devices. Results show that for a gain controlled LNA circuit, with 48 specification parameters, it is possible to achieve 67% improvement in test quality for the same test time or 19.2% test time reduction with the same test quality compared to the widely used set cover method.
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U2 - 10.1109/ICCD.2008.4751866
DO - 10.1109/ICCD.2008.4751866
M3 - Conference contribution
AN - SCOPUS:62349138241
SN - 9781424426584
T3 - 26th IEEE International Conference on Computer Design 2008, ICCD
SP - 227
EP - 233
BT - 26th IEEE International Conference on Computer Design 2008, ICCD
T2 - 26th IEEE International Conference on Computer Design 2008, ICCD
Y2 - 12 October 2008 through 15 October 2008
ER -