Dynamic test scheduling for analog circuits for improved test quality

Ender Yilmaz, Sule Ozev

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

In this paper, we present an innovative test scheduling method to improve test quality and/or reduce test time for analog circuits. Our dynamic test scheduling approach predicts the fail probability of unmeasured specifications with the aim of passing statistically well-behaved chips early on so as to devote more resources to marginal devices. Results show that for a gain controlled LNA circuit, with 48 specification parameters, it is possible to achieve 67% improvement in test quality for the same test time or 19.2% test time reduction with the same test quality compared to the widely used set cover method.

Original languageEnglish (US)
Title of host publication26th IEEE International Conference on Computer Design 2008, ICCD
Pages227-233
Number of pages7
DOIs
StatePublished - 2008
Event26th IEEE International Conference on Computer Design 2008, ICCD - Lake Tahoe, CA, United States
Duration: Oct 12 2008Oct 15 2008

Other

Other26th IEEE International Conference on Computer Design 2008, ICCD
CountryUnited States
CityLake Tahoe, CA
Period10/12/0810/15/08

Fingerprint

Analog circuits
Scheduling
Specifications
Networks (circuits)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Yilmaz, E., & Ozev, S. (2008). Dynamic test scheduling for analog circuits for improved test quality. In 26th IEEE International Conference on Computer Design 2008, ICCD (pp. 227-233). [4751866] https://doi.org/10.1109/ICCD.2008.4751866

Dynamic test scheduling for analog circuits for improved test quality. / Yilmaz, Ender; Ozev, Sule.

26th IEEE International Conference on Computer Design 2008, ICCD. 2008. p. 227-233 4751866.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yilmaz, E & Ozev, S 2008, Dynamic test scheduling for analog circuits for improved test quality. in 26th IEEE International Conference on Computer Design 2008, ICCD., 4751866, pp. 227-233, 26th IEEE International Conference on Computer Design 2008, ICCD, Lake Tahoe, CA, United States, 10/12/08. https://doi.org/10.1109/ICCD.2008.4751866
Yilmaz E, Ozev S. Dynamic test scheduling for analog circuits for improved test quality. In 26th IEEE International Conference on Computer Design 2008, ICCD. 2008. p. 227-233. 4751866 https://doi.org/10.1109/ICCD.2008.4751866
Yilmaz, Ender ; Ozev, Sule. / Dynamic test scheduling for analog circuits for improved test quality. 26th IEEE International Conference on Computer Design 2008, ICCD. 2008. pp. 227-233
@inproceedings{588547a5fce04353be5aa45c0fee49b8,
title = "Dynamic test scheduling for analog circuits for improved test quality",
abstract = "In this paper, we present an innovative test scheduling method to improve test quality and/or reduce test time for analog circuits. Our dynamic test scheduling approach predicts the fail probability of unmeasured specifications with the aim of passing statistically well-behaved chips early on so as to devote more resources to marginal devices. Results show that for a gain controlled LNA circuit, with 48 specification parameters, it is possible to achieve 67{\%} improvement in test quality for the same test time or 19.2{\%} test time reduction with the same test quality compared to the widely used set cover method.",
author = "Ender Yilmaz and Sule Ozev",
year = "2008",
doi = "10.1109/ICCD.2008.4751866",
language = "English (US)",
isbn = "9781424426584",
pages = "227--233",
booktitle = "26th IEEE International Conference on Computer Design 2008, ICCD",

}

TY - GEN

T1 - Dynamic test scheduling for analog circuits for improved test quality

AU - Yilmaz, Ender

AU - Ozev, Sule

PY - 2008

Y1 - 2008

N2 - In this paper, we present an innovative test scheduling method to improve test quality and/or reduce test time for analog circuits. Our dynamic test scheduling approach predicts the fail probability of unmeasured specifications with the aim of passing statistically well-behaved chips early on so as to devote more resources to marginal devices. Results show that for a gain controlled LNA circuit, with 48 specification parameters, it is possible to achieve 67% improvement in test quality for the same test time or 19.2% test time reduction with the same test quality compared to the widely used set cover method.

AB - In this paper, we present an innovative test scheduling method to improve test quality and/or reduce test time for analog circuits. Our dynamic test scheduling approach predicts the fail probability of unmeasured specifications with the aim of passing statistically well-behaved chips early on so as to devote more resources to marginal devices. Results show that for a gain controlled LNA circuit, with 48 specification parameters, it is possible to achieve 67% improvement in test quality for the same test time or 19.2% test time reduction with the same test quality compared to the widely used set cover method.

UR - http://www.scopus.com/inward/record.url?scp=62349138241&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=62349138241&partnerID=8YFLogxK

U2 - 10.1109/ICCD.2008.4751866

DO - 10.1109/ICCD.2008.4751866

M3 - Conference contribution

SN - 9781424426584

SP - 227

EP - 233

BT - 26th IEEE International Conference on Computer Design 2008, ICCD

ER -