Dynamic and leakage power reduction of ASICs using configurable threshold logic gates

Jinghua Yang, Joseph Davis, Niranjan Kulkarni, Jae-sun Seo, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

This article demonstrates an unconventional approach to computing logic functions for use in ASICs, and a fully automated approach to technology mapping for standard cell ASICs using the new cells. The approach results in a significant reduction in power, leakage, area and wire-length, without sacrificing performance of the design. At the heart of this approach is a configurable threshold logic gate. Using a standard cell library of such gates, a new technology mapping algorithm is applied to automatically transform a given netlist into one with an optimal mixture of conventional logic gates and threshold gates. The mapping algorithm is based on logic decomposition of Boolean functions into specific threshold functions. This approach was used to fabricate a 32-bit signed 2-stage Wallace-Tree multiplier in a 65-nm LP technology. Simulation and chip measurement results of the multiplier show a 33% improvement in dynamic power at 30% switching activity, 24% lower core area, 45% lower wire-length and 50% lower leakage without any performance degradation, compared to a functionally equivalent, conventional standard cell implementation. Similar results are shown for a FIR filter, a 32-bit MIPS, a 128-bit AES encryption circuit and a floating-point multiplier.

Original languageEnglish (US)
Title of host publication2015 IEEE Custom Integrated Circuits Conference, CICC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479986828
DOIs
StatePublished - Nov 25 2015
EventIEEE Custom Integrated Circuits Conference, CICC 2015 - San Jose, United States
Duration: Sep 28 2015Sep 30 2015

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2015-November
ISSN (Print)0886-5930

Other

OtherIEEE Custom Integrated Circuits Conference, CICC 2015
CountryUnited States
CitySan Jose
Period9/28/159/30/15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Yang, J., Davis, J., Kulkarni, N., Seo, J., & Vrudhula, S. (2015). Dynamic and leakage power reduction of ASICs using configurable threshold logic gates. In 2015 IEEE Custom Integrated Circuits Conference, CICC 2015 [7338369] (Proceedings of the Custom Integrated Circuits Conference; Vol. 2015-November). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2015.7338369