Abstract
In this paper we present an architecture for a 2-D Discrete Wavelet Transform (DWT)-based encoder that handles computations along the border efficiently by using the method of symmetric extension. We choose symmetric extension (SA) as opposed to zero padding or periodic extension since (i) the coefficients generated by SA can be used to obtain perfect reconstruction and (ii) it is better suited for low bit rate coders. The proposed architecture is similar to the existing 2-D DWT architectures for zero padded images with the notable exception that additional router units are now required to reorder the data. Reordering is essential to sustain the computation of successive problem instances in symmetrically extended images. We show that the router can be implemented using simple combinational logic, resulting in minimal area overhead.
| Original language | English (US) |
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| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Publisher | IEEE |
| Volume | 4 |
| State | Published - 1999 |
| Event | Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 - Orlando, FL, USA Duration: May 30 1999 → Jun 2 1999 |
Other
| Other | Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 |
|---|---|
| City | Orlando, FL, USA |
| Period | 5/30/99 → 6/2/99 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials