Aging due to bias-temperature-instability (BTI) is the dominant cause of functional failure in large scale logic circuits. Power efficient techniques such as clock gating or dynamic voltage scaling exacerbate the problem of asymmetric aging. Traditional analysis on synchronous circuits focuses on shift in data path delay and neglects the change in duty cycle. This work highlights the impact of NBTI and PBTI at advanced technology node on duty cycle shift which is important for edge triggered designs, such as latch based circuits. The contributions of this work are: (1) characterization, decoupling and model calibration of NBTI, PBTI and CHC data at 28nm HK-MG technology; (2) demonstration of monotonic shift of duty cycle under static stress condition and non-monotonic shift under dynamic stress, in which duty cycle converges to 50%. Additional PBTI component at 28nm HK-MG causes faster shift in duty cycle compared to conventional NBTI aging; (3) the sensitivity of long-term aging to the ratio between static and dynamic stress conditions. With PBTI, duty cycle shift is effectively reduced by dynamic stress.