TY - GEN
T1 - Duty compensated reduced harmonic control for a single-phase H-bridge PFC converter
AU - Sankar, U. Arun
AU - Mallik, Ayan
AU - Khaligh, Alireza
N1 - Funding Information:
This work has been sponsored partly by the National Science Foundation Grant Numbers 1507546 and 1602012, which are gratefully acknowledged.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/4/18
Y1 - 2018/4/18
N2 - A power factor correction (PFC) circuit is an essential requirement for AC-DC conversion to meet the strict grid quality standards. High efficiency and increased power density requirements have driven the industry towards bridgeless PFC circuits as a viable solution for front end rectification. Inherent electro magnetic interference (EMI) issues of an H-Bridge PFC topology has hindered the adaptation of this circuit. In this paper, a duty compensation method is proposed to reduce the harmonic content generated by switch node of an H-Bridge topology. The proposed control technique reduces the generated harmonics without addition of any hardware components helping to meet high power density requirements. A 1kW SiC-based laboratory prototype is designed to verify the proposed control technique. The experimental results show that an input power factor of 0.99 with a conversion efficiency of 96.5% and total harmonic distortion (THD) of 2.05 % can be achieved.
AB - A power factor correction (PFC) circuit is an essential requirement for AC-DC conversion to meet the strict grid quality standards. High efficiency and increased power density requirements have driven the industry towards bridgeless PFC circuits as a viable solution for front end rectification. Inherent electro magnetic interference (EMI) issues of an H-Bridge PFC topology has hindered the adaptation of this circuit. In this paper, a duty compensation method is proposed to reduce the harmonic content generated by switch node of an H-Bridge topology. The proposed control technique reduces the generated harmonics without addition of any hardware components helping to meet high power density requirements. A 1kW SiC-based laboratory prototype is designed to verify the proposed control technique. The experimental results show that an input power factor of 0.99 with a conversion efficiency of 96.5% and total harmonic distortion (THD) of 2.05 % can be achieved.
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U2 - 10.1109/APEC.2018.8341291
DO - 10.1109/APEC.2018.8341291
M3 - Conference contribution
AN - SCOPUS:85046961214
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 1996
EP - 2000
BT - APEC 2018 - 33rd Annual IEEE Applied Power Electronics Conference and Exposition
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 33rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2018
Y2 - 4 March 2018 through 8 March 2018
ER -