Duty compensated reduced harmonic control for a single-phase H-bridge PFC converter

U. Arun Sankar, Ayan Mallik, Alireza Khaligh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

A power factor correction (PFC) circuit is an essential requirement for AC-DC conversion to meet the strict grid quality standards. High efficiency and increased power density requirements have driven the industry towards bridgeless PFC circuits as a viable solution for front end rectification. Inherent electro magnetic interference (EMI) issues of an H-Bridge PFC topology has hindered the adaptation of this circuit. In this paper, a duty compensation method is proposed to reduce the harmonic content generated by switch node of an H-Bridge topology. The proposed control technique reduces the generated harmonics without addition of any hardware components helping to meet high power density requirements. A 1kW SiC-based laboratory prototype is designed to verify the proposed control technique. The experimental results show that an input power factor of 0.99 with a conversion efficiency of 96.5% and total harmonic distortion (THD) of 2.05 % can be achieved.

Original languageEnglish (US)
Title of host publicationAPEC 2018 - 33rd Annual IEEE Applied Power Electronics Conference and Exposition
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1996-2000
Number of pages5
ISBN (Electronic)9781538611807
DOIs
StatePublished - Apr 18 2018
Externally publishedYes
Event33rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2018 - San Antonio, United States
Duration: Mar 4 2018Mar 8 2018

Publication series

NameConference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
Volume2018-March

Other

Other33rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2018
CountryUnited States
CitySan Antonio
Period3/4/183/8/18

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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