TY - JOUR
T1 - Digital Fault-based Built-in Self-test and Evaluation of Low Dropout Voltage Regulators
AU - Ince, Mehmet
AU - Bilgic, Bora
AU - Ozev, Sule
N1 - Funding Information:
This work is supported by the National Science Foundation by Contract Number CCF-1617562 and the Semiconductor Research Corporation with Task Number 2810.044. Authors’ address: M. Ince, B. Bilgic, and S. Ozev, Arizona State University, Tempe, AZ; emails: {mehmet.ince, bbilgic, Sule.Ozev}@asu.edu. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. © 2022 Association for Computing Machinery. 1550-4832/2022/08-ART54 $15.00 https://doi.org/10.1145/3510852
Publisher Copyright:
© 2022 Association for Computing Machinery.
PY - 2022/7
Y1 - 2022/7
N2 - With increasing pressure to obtain near-zero defect rates, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, power converters, and data converters. This article presents an extremely low-cost built-in self-test technique for LDOs, specifically designed for fault detection. The methodology relies on exciting the LDO loop at the voltage reference input via a pseudo-random signal with white noise characteristics and observing the response from the output of LDO via all-digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with an LDO as a device under test is designed in 65nm technology. Fault simulations performed at the transistor level show that all resistive open/short defects in circuit components can be detected even if they do not cause a catastrophic failure in the LDO response. The proposed technique is validated with hardware using off-the-shelf components.
AB - With increasing pressure to obtain near-zero defect rates, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, power converters, and data converters. This article presents an extremely low-cost built-in self-test technique for LDOs, specifically designed for fault detection. The methodology relies on exciting the LDO loop at the voltage reference input via a pseudo-random signal with white noise characteristics and observing the response from the output of LDO via all-digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with an LDO as a device under test is designed in 65nm technology. Fault simulations performed at the transistor level show that all resistive open/short defects in circuit components can be detected even if they do not cause a catastrophic failure in the LDO response. The proposed technique is validated with hardware using off-the-shelf components.
KW - built-in self test
KW - linear dropout regulators
KW - Mixed signal circuit testing
KW - pseudo random binary sequence
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U2 - 10.1145/3510852
DO - 10.1145/3510852
M3 - Article
AN - SCOPUS:85137168504
SN - 1550-4832
VL - 18
JO - ACM Journal on Emerging Technologies in Computing Systems
JF - ACM Journal on Emerging Technologies in Computing Systems
IS - 3
M1 - 54
ER -