TY - GEN
T1 - Digital Defect Based Built-in Self-Test for Low Dropout Voltage Regulators
AU - Ince, Mehmet
AU - Ozev, Sule
N1 - Funding Information:
This work is supported by National Science Foundation by Contract Number CCF-1617562 and the Semiconductor Research Corporation with Task Number 2810.044
Publisher Copyright:
© 2020 IEEE.
PY - 2020/5
Y1 - 2020/5
N2 - With the increasing complexity of electronic components in critical applications, pressure on single components to have zero defects is also increasing. Thus there is a need to explore built-in self-test and other non-traditional test techniques for mixed-signal circuits, such as data converters, phase locked loops and power converters. In this paper, we present an extremely low cost, digital built-in self-test methodology for Low Dropout Regulators (LDO), specifically used for defect detection. The technique relies on perturbing the LDO loop at the reference voltage input via pseudo random binary sequence which has white noise characteristics and cross correlating the output of LDO with input excitation using only digital circuits, thus inducing low power and area overhead. The built-in self-test technique together with an LDO is designed using 65nm TMSC technology. Transistor level structural fault simulations display that all inserted faults can be detected even if they do not change the DC level of the LDO output.
AB - With the increasing complexity of electronic components in critical applications, pressure on single components to have zero defects is also increasing. Thus there is a need to explore built-in self-test and other non-traditional test techniques for mixed-signal circuits, such as data converters, phase locked loops and power converters. In this paper, we present an extremely low cost, digital built-in self-test methodology for Low Dropout Regulators (LDO), specifically used for defect detection. The technique relies on perturbing the LDO loop at the reference voltage input via pseudo random binary sequence which has white noise characteristics and cross correlating the output of LDO with input excitation using only digital circuits, thus inducing low power and area overhead. The built-in self-test technique together with an LDO is designed using 65nm TMSC technology. Transistor level structural fault simulations display that all inserted faults can be detected even if they do not change the DC level of the LDO output.
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U2 - 10.1109/ETS48528.2020.9131577
DO - 10.1109/ETS48528.2020.9131577
M3 - Conference contribution
AN - SCOPUS:85089137149
T3 - Proceedings of the European Test Workshop
BT - Proceedings - 2020 IEEE European Test Symposium, ETS 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 IEEE European Test Symposium, ETS 2020
Y2 - 25 May 2020 through 29 May 2020
ER -