Digital CMOS neuromorphic processor design featuring unsupervised online learning

Jae-sun Seo, Mingoo Seok

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

The compute-intensive and power-efficient brain has been a source of inspiration for a broad range of neural networks to solve recognition and classification tasks. Compared to the supervised deep neural networks (DNNs) that have been very successful on well-defined labeled datasets, bio-plausible spiking neural networks (SNNs) with unsupervised learning rules could be well-suited for training and learning representations from the massive amount of unlabeled data. To design dense and low-power hardware for such unsupervised SNNs, we employ digital CMOS circuits for neuromorphic processors, which can exploit transistor scaling and dynamic voltage scaling to the utmost. As exemplary works, we present two neuromorphic processor designs. First, a 45nm neuromorphic chip is designed for a small-scale network of spiking neurons. Through tight integration of memory (64k SRAM synapses) and computation (256 digital neurons), the chip demonstrates on-chip learning on pattern recognition tasks down to 0.53V supply. Secondly, a 65nm neuromorphic processor that performs unsupervised on-line spike-clustering for brain sensing applications is implemented with 1.2k digital neurons and 4.7k latch-based synapses. The processor exhibits a power consumption of 9.3μW/ch at 0.3V supply. Synapse hardware precision, efficient synapse memory array access, overfitting, and voltage scaling will be discussed for dense and power-efficient on-chip learning for CMOS spiking neural networks.

Original languageEnglish (US)
Title of host publication2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015
PublisherIEEE Computer Society
Pages49-51
Number of pages3
ISBN (Electronic)9781467391405
DOIs
StatePublished - Oct 30 2015
Event23rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015 - Daejeon, Korea, Republic of
Duration: Oct 5 2015Oct 7 2015

Publication series

NameIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
Volume2015-October
ISSN (Print)2324-8432
ISSN (Electronic)2324-8440

Other

Other23rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015
CountryKorea, Republic of
CityDaejeon
Period10/5/1510/7/15

Keywords

  • CMOS
  • digital circuits
  • low-power
  • low-voltage
  • neuromorphic computing
  • on-chip learning
  • spiking neural networks
  • unsupervised learning

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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  • Cite this

    Seo, J., & Seok, M. (2015). Digital CMOS neuromorphic processor design featuring unsupervised online learning. In 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015 (pp. 49-51). [7314390] (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; Vol. 2015-October). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2015.7314390